devel/llvm[789]: restore arm_bf16.h to ARM backend

arm_bf16.h is generated for both armv7 and aarch64 so move it back to
ARM.  We don't support AArch64 without ARM so we can just move it and
not need to worry about duplicate supression (I'd previously fixed the
issue in llvm19 in a more complicated manner so this change removes the
duplicate supression and documents why it's not needed.)

PR:		281179
Reported by:	Mark Millard

devel/llvm17/Makefile

 PORTNAME=	llvm
 DISTVERSION=	17.0.6
-PORTREVISION=	7
+PORTREVISION=	8
 CATEGORIES=	devel lang
 MASTER_SITES=	https://github.com/llvm/llvm-project/releases/download/llvmorg-${DISTVERSION:S/rc/-rc/}/ \
 		https://${PRE_}releases.llvm.org/${LLVM_RELEASE}${RCDIR}/
@@ -375,11 +375,14 @@ NATIVE_BACKENDS+=	WebAssembly
 STANDARD_BACKENDS=	${_FREEBSD_BACKENDS} AMDGPU AVR BPF Hexagon Lanai \
 			LoongArch MSP430 NVPTX SystemZ VE WebAssembly XCore
 _BE_LIBS_COMMON=	CodeGen Desc Info
-_BE_INCS_AArch64=	arm_bf16.h arm_sme_draft_spec_subject_to_change.h
+_BE_INCS_AArch64=	arm_sme_draft_spec_subject_to_change.h
 _BE_LIBS_AArch64=	AsmParser Disassembler Utils
 _BE_LIBS_BACKWARDS_AArch64=Exegesis
 _BE_LIBS_AMDGPU=	AsmParser Disassembler TargetMCA Utils
-_BE_INCS_ARM=		arm_cde.h arm_fp16.h arm_mve.h arm_neon.h arm_sve.h
+# XXX: some of these are for both ARM and AArch64, but we don't provide
+# a mechanism to build AArch64 without ARM so we avoid duplication by
+# listing them here.
+_BE_INCS_ARM=		arm_bf16.h arm_cde.h arm_fp16.h arm_mve.h arm_neon.h arm_sve.h
 _BE_LIBS_ARM=		AsmParser Disassembler Utils
 _BE_LIBS_AVR=		AsmParser Disassembler
 _BE_LIBS_BPF=		AsmParser Disassembler

devel/llvm18/Makefile

 PORTNAME=	llvm
 DISTVERSION=	18.1.8
-PORTREVISION=	1
+PORTREVISION=	2
 CATEGORIES=	devel lang
 MASTER_SITES=	https://github.com/llvm/llvm-project/releases/download/llvmorg-${DISTVERSION:S/rc/-rc/}/
 PKGNAMESUFFIX=	${LLVM_SUFFIX}
@@ -374,12 +374,14 @@ NATIVE_BACKENDS+=	WebAssembly
 STANDARD_BACKENDS=	${_FREEBSD_BACKENDS} AMDGPU AVR BPF Hexagon Lanai \
 			LoongArch MSP430 NVPTX SystemZ VE WebAssembly XCore
 _BE_LIBS_COMMON=	CodeGen Desc Info
-_BE_INCS_AArch64=	arm_bf16.h
 _BE_LIBS_AArch64=	AsmParser Disassembler Utils
 _BE_LIBS_BACKWARDS_AArch64=Exegesis
 _BE_LIBS_AMDGPU=	AsmParser Disassembler TargetMCA Utils
-_BE_INCS_ARM=		arm_cde.h arm_fp16.h arm_mve.h arm_neon.h arm_sme.h \
-			arm_sve.h arm_vector_types.h
+# XXX: some of these are for both ARM and AArch64, but we don't provide
+# a mechanism to build AArch64 without ARM so we avoid duplication by
+# listing them here.
+_BE_INCS_ARM=		arm_bf16.h arm_cde.h arm_fp16.h arm_mve.h arm_neon.h \
+			arm_sme.h arm_sve.h arm_vector_types.h
 _BE_LIBS_ARM=		AsmParser Disassembler Utils
 _BE_LIBS_AVR=		AsmParser Disassembler
 _BE_LIBS_BPF=		AsmParser Disassembler

devel/llvm19/Makefile

@@ -391,10 +391,12 @@ NATIVE_BACKENDS+=	WebAssembly
 STANDARD_BACKENDS=	${_FREEBSD_BACKENDS} AMDGPU AVR BPF Hexagon Lanai \
 			LoongArch MSP430 NVPTX SystemZ VE WebAssembly XCore
 _BE_LIBS_COMMON=	CodeGen Desc Info
-_BE_INCS_AArch64=	arm_bf16.h
 _BE_LIBS_AArch64=	AsmParser Disassembler Utils
 _BE_LIBS_BACKWARDS_AArch64=Exegesis
 _BE_LIBS_AMDGPU=	AsmParser Disassembler TargetMCA Utils
+# XXX: some of these are for both ARM and AArch64, but we don't provide
+# a mechanism to build AArch64 without ARM so we avoid duplication by
+# listing them here.
 _BE_INCS_ARM=		arm_bf16.h arm_cde.h arm_fp16.h arm_mve.h arm_neon.h \
 			arm_sme.h arm_sve.h arm_vector_types.h
 _BE_LIBS_ARM=		AsmParser Disassembler Utils
@@ -423,10 +425,9 @@ _BE_LIBS_XCore=		Disassembler
 _BE_LIBS_${BE}+=	${_BE_LIBS_COMMON:S/^/${BE_ARCH}/} \
 			${_BE_LIBS_${BE_ARCH}:S/^/${BE_ARCH}/} \
 			${_BE_LIBS_BACKWARDS_${BE_ARCH}:S/$/${BE_ARCH}/}
-__BE_INCS_${BE}+=	${_BE_INCS_${BE_ARCH}}
+_BE_INCS_${BE}+=	${_BE_INCS_${BE_ARCH}}
 _BE_MODS_${BE}+=	${_BE_MODS_${BE_ARCH}}
 .endfor
-_BE_INCS_${BE}=		${__BE_INCS_${BE}:O:u}
 .endfor
 BE_PATTERN=LLVM(${_BE_LIBS_STANDARD:O:S/$/.a/:ts|})|${_BE_INCS_STANDARD:ts|}|${_BE_MODS_STANDARD:ts|}