cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/SystemVerilog

cad/Makefile

@@ -111,6 +111,7 @@
     SUBDIR += py-pyfda
     SUBDIR += py-pygmsh
     SUBDIR += py-pymtl
+    SUBDIR += py-vunit-hdl
     SUBDIR += python-gdsii
     SUBDIR += qcad
     SUBDIR += qcsxcad

cad/py-vunit-hdl/Makefile

+PORTNAME=	vunit-hdl
+DISTVERSION=	4.6.0
+CATEGORIES=	cad python
+MASTER_SITES=	CHEESESHOP
+PKGNAMEPREFIX=	${PYTHON_PKGNAMEPREFIX}
+DISTNAME=	${PORTNAME:S/-/_/}-${PORTVERSION}
+
+MAINTAINER=	yuri@FreeBSD.org
+COMMENT=	Open source unit testing framework for VHDL/SystemVerilog
+WWW=		https://vunit.github.io/
+
+LICENSE=	MPL20
+
+RUN_DEPENDS=	${PYTHON_PKGNAMEPREFIX}colorama>0:devel/py-colorama@${PY_FLAVOR}
+
+USES=		python:3.6+
+USE_PYTHON=	distutils autoplist pytest # 2 tests fail, see https://github.com/VUnit/vunit/issues/886
+
+NO_ARCH=	yes
+
+.include <bsd.port.mk>

cad/py-vunit-hdl/distinfo

+TIMESTAMP = 1673167323
+SHA256 (vunit_hdl-4.6.0.tar.gz) = b405a97b5da4c26c99d8c726f38594c9173c0ac3f8a0832431c8e4920d2cacdf
+SIZE (vunit_hdl-4.6.0.tar.gz) = 626992

cad/py-vunit-hdl/pkg-descr

+VUnit is an open source unit testing framework for VHDL/SystemVerilog. It
+features the functionality needed to realize continuous and automated
+testing of your HDL code. VUnit doesn't replace but rather complements
+traditional testing methodologies by supporting a test early and often
+approach through automation. Read more about VUnit.