Commit fbef1724 authored by Alan Wood's avatar Alan Wood

Added rotation

parent 70447ad9
......@@ -65,4 +65,16 @@ assign y2 = a2 >>> 1; // Arithemtic MSB sign bit shifted in
assign y2 = a2 << 1; // Logical shift left same result as
assign y2 = a2 <<< 1; // Arithmetic shift left
```
\ No newline at end of file
```
## Rotation
### Rotate right 1 bit
```verilog
assign y3 = {y3[0],y3[2]:1};
```
### Rotate right 2 bit
```verilog
assign y3 = {y3[1:0],y3[2]};
```
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment