Commit be3b1d17 authored by Alan Wood's avatar Alan Wood

Added concatenation/replication

parent c640c841
......@@ -35,9 +35,22 @@ assign y = a ^ b;
## Reduction
```verilog
assign y = | a4
assign y = | a4;
```
### is equivelent to:
```verilog
assign y = a[1] | a[0];
```
\ No newline at end of file
```
## Concatenation and Replication
```verilog
assign y2 = {a,b};
assign y2 = {a,1'b0};
assign y3 = {a,b,1'b1};
assign y3 = {a,2'b10};
assign y3 = {a,a2};
assign y3 = {a,a2[0],1'b1};
assign {y2,y} = {y3[1:0],a};
assign y3 = {a,2{1'b1'}};
```
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