Commit bd5a1bac authored by Alan Wood's avatar Alan Wood

Added Procedural blocks

parent aec729c5
......@@ -137,4 +137,33 @@ assign y = (a == 2'b00) ? 1'b0:
1'bx; // i == 2'b11
```
## Behavioural Blocks
Procedural blocks using always block, these black box sections describe behaviour using
procedural statements, always behavioural blocks are defined with an event control
expression or sensitivity list
```verilog
always @(sensitivity list)
begin [Optional label]
[optional local variable declerations];
[proceduaral statements];
end [optional label]
```
### Procedual Assignment
```verilog
[varialble] = [expression]; // blocking, assigned beforee next statement like normal C
[varialble] <= [expression]; // non blocking, assigned at end of always block
```
blocking tends to be used for combinational circuits, non-blocking for sequential
In a procedural assignment, an expression can only be assigned to an output with
one of the variable data types, which are reg, integer, real, time, and realtime.
The reg data type is like the wire data type but used with a procedural output.
The integer data type represents a fixed-size (usually 32 bits) signed number in
2's-complement format. Since its size is fixed, we usually don't use it in synthesis.
The other data types are for modeling and simulation and cannot be synthesized
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment