Commit aec729c5 authored by Alan Wood's avatar Alan Wood

Added Conditionals,and Z/X values

parent a8ac0ad5
......@@ -80,7 +80,9 @@ assign y3 = {y3[1:0],y3[2]};
```
## Operator precedence
```verilog
!,~,+,-(uni),**,*,/,%,+,-(bin),>>,<<,>>>,<<<,==,!=,===,!==,&,^,|,&&,||,?: */
````
## Conditionals
......@@ -112,5 +114,27 @@ else
begin
// else code
end
```
\ No newline at end of file
```
## Synthesis of Z and X Values
Z values can only be synthesised by tristate
bufferes and thus infer them these have output enable inputs to control their
output state for example here is a single bit trastate buffer with an output enable
```verilog
assign y = (oen) ? a : 1'bz;
```
This sort of construuct is useful for biderectional ports or buses.
The synthesis of X is don't care, the value may be either 0 or 1, this can
improve the efficiency or optimisation of combinational circuits
```verilog
assign y = (a == 2'b00) ? 1'b0:
(a == 2'b01) ? 1'b1:
(a == 2'b10) ? 1'b1:
1'bx; // i == 2'b11
```
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