Commit a8ac0ad5 authored by Alan Wood's avatar Alan Wood

Added conditionals

parent fbef1724
......@@ -78,3 +78,39 @@ assign y3 = {y3[0],y3[2]:1};
```verilog
assign y3 = {y3[1:0],y3[2]};
```
## Operator precedence
!,~,+,-(uni),**,*,/,%,+,-(bin),>>,<<,>>>,<<<,==,!=,===,!==,&,^,|,&&,||,?: */
## Conditionals
### Tertiary
```verilog
assign max = (a > b) ? a : b;
```
## If/Else
```verilog
if(a < b)
assign min = a;
else
assign min = b;
```
```verilog
if(boolean)
// if code
else if (boolean)
// if else 1 code
else
// else code
```
```verilog
if(boolean)
begin
// begin code
end
else
begin
// else code
end
```
\ No newline at end of file
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