Commit 99f029aa authored by Alan Wood's avatar Alan Wood

Added Assignment description, emphasising it's continous and concurrent nature

parent b6f29793
......@@ -10,6 +10,14 @@ wire input a2[1:0],b2[1:0];
wire output y2[1:0];
wire output y3[2:0];
```
## Assignment
An assign statement is used for modeling only combinational logic and it is executed continuously. So the assign statement is called 'continuous assignment statement' as there is no sensitive list (see always blocks later).
```verilog
assign y = a;
```
## Logic bitwise primitives
......
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