Commit 65dd3e62 authored by Andrew Richards's avatar Andrew Richards

Some comments added

Added some comments to clarify behaviour of some code esp. for
a newbie
parent 26852cbd
......@@ -52,14 +52,14 @@ assign y = a2[1] | a2[0];
## Concatenation and Replication
```verilog
assign y2 = {a,b};
assign y2 = {a,1'b0};
assign y3 = {a,b,1'b1};
assign y3 = {a,2'b10};
assign y3 = {a,a2};
assign y3 = {a,a2[0],1'b1};
assign {y2,y} = {y3[1:0],a};
assign y3 = {a,2{1'b1}};
assign y2 = {a,b}; // creates a 2-bit signal of a with b
assign y2 = {a,1'b0}; // a with 1 bit binary 0 (constant)
assign y3 = {a,b,1'b1}; // a with b with binary 1 (constant)
assign y3 = {a,2'b10}; // a with 2 binary bits 1, 0
assign y3 = {a,a2}; // a with a2 (a2 is 2 bits)
assign y3 = {a,a2[0],1'b1}; // a with single bit from a2 with 1
assign {y2,y} = {y3[1:0],a}; // multiple assignment: creates y2 as 2 bits from y3 and y as a
assign y3 = {a,2{1'b1}}; // a with 2 lots of binary 1
```
## Shifting
......@@ -104,6 +104,8 @@ assign max = (a > b) ? a : b;
## If/Else
(NB not sequential, actually 'network routings')
```verilog
if(a < b)
assign min = a;
......@@ -122,7 +124,7 @@ else
```verilog
if(boolean)
begin
begin // need begin...end if >1 line of code within condition
// begin code
end
else
......@@ -194,7 +196,7 @@ A register is simple memory wire to hold state, normally implemented as
D-Types
```verilog
output reg
output reg // single-bit, use [] syntax above for >1 bit registers
```
## Conditional Examples
......@@ -212,7 +214,7 @@ en a1 a2 y
```verilog
module pri_encoder
(
( // 4 bit input, 3 bit output
input wire [4:1] r,
output wire [2:0] y
)
......@@ -239,9 +241,9 @@ module decoder_1
input wire en,
output reg [3:0] y
)
always @*
always @* // @* means 'Anything needed'; clearer to list required resources but danger of missing items
if(~en)
y = 4'b0000;
y = 4'b0000; // 4-bit wide, binary representation: 0000
else if(a == 2'b00)
y = 4'b0001;
else if(a == 2'b01)
......@@ -338,7 +340,7 @@ module decoder_4
always @*
casez ({en,a})
3'b0??: y = 4'b0000;
3'b0??: y = 4'b0000; // casez also offers '?'
3'b100: y = 4'b0001;
3'b101: y = 4'b0010;
3'b110: y = 4'b0100;
......@@ -473,21 +475,21 @@ endcase
## Adder with carry
```verilog
module adder #(parameter N=4)
module adder #(parameter N=4) // input parameter N, default value of 4 if not specified. N will be the adder width here
(
input wire [N-1:0] a,b,
output wire [N-1:0] sum,
output wire cout
output wire cout // carry bit
);
/* Constant Declaration */
localparam N1 = N-1;
localparam N1 = N-1; // localparam: only visible within module
/* Signal Declaration */
wire [N:0] sum_ext;
wire [N:0] sum_ext; // NB not N-1
/* module body */
assign sum_ext = {1'b0, a} + {1'b0, b};
assign sum_ext = {1'b0, a} + {1'b0, b}; // excludes Nth bit
assign sum = sum_ext[N1:0];
assign cout = sum_ext[N];
......@@ -499,7 +501,7 @@ module adder_example
output wire [3:0] sum4,
output wire c4
)
// Instantiate a 4 bit adder
// Instantiate a 4 bit adder - .N specifies parameter name N; connect a to a4, b to b4, sum to sum4, cout to c4
adder #(.N(4)) four_bit_adder (.a(a4), .b(b4), .sum(sum4), .cout(c4));
endmodule
......
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