Commit 5fe9fa5e by Alan Wood

Added Functions and mentioned tasks

parent 99f029aa
......@@ -358,6 +358,25 @@ endmodule
In casez, the `?` is used to indicate either X or Z state.
## Tasks & Functions
Tasks and Functions are used when a set of operations are commonly repeated and used, this save you writing the same thing out over and over a gain. Functions can only be used for modelling combinational logic cannot drive more than one output and cannot contain delays, unlike tasks which can. Tasks also can not return a value unlike functions which can.
Below shows a function for calculating parity, something that may be used frequently in digital logic design.
```verilog
function parity;
input [31:0] data;
integer i;
begin
parity = 0;
for (i= 0; i < 32; i = i + 1) begin
parity = parity ^ data[i];
end
end
endfunction
```
## Common Errors
* Variable assigned in multiple always blocks
......
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