Commit 45f840b3 authored by Alan Wood's avatar Alan Wood

Added some simple verilog comments for the example

parent 8cf4809d
......@@ -13,6 +13,13 @@
* *
******************************************************************************/
/** Simple clocked PWM
* PARAM CTR_LEN : sets bit depth of PWM
* clk : Clock
* rst : Reset
* compare : sets threshold for compare match as ctr counts up
* pwm : output wire for pwm signal
*/
module pwm #(parameter CTR_LEN = 8) (
input clk,
input rst,
......
......@@ -12,7 +12,15 @@
* permissions and limitations under the License. *
* *
******************************************************************************/
/** Simple addressed shift registers
* Param ADDR_LEN : bit width for address
* Param DATA_LEN : bit width for register/data width
* sck : clock
* si : Serial data in
* cs : Chip select in
* addr : address register
* data : data register
*/
module shiftreg #(parameter ADDR_LEN = 8, parameter DATA_LEN = 8 ) (
input sck,
input si,
......@@ -31,9 +39,6 @@ module shiftreg #(parameter ADDR_LEN = 8, parameter DATA_LEN = 8 ) (
end
assign {data,addr} = sr;
// always @(posedge cs) begin
// {data,addr} = sr;
// end
endmodule
......@@ -13,6 +13,9 @@
* *
******************************************************************************/
/** Serial addressed shift registers used for simple PWM
*
*/
module SPI_PWM(
// 50MHz clock input
input clk,
......@@ -22,7 +25,6 @@ module SPI_PWM(
input cs,
// Outputs to the 8 onboard LEDs
output[51:0]PMOD,
//output mypwm
);
localparam p = 4;
......@@ -36,8 +38,7 @@ wire [7:0] addr, val;
shiftreg mysr (
//100Mhz clock
.sck(sck),
//.rst(rst),
// .blink(LED[0])
//.rst(rst), to implement
.cs(cs),
.si(mosi),
.addr(addr),
......
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