Commit 29c05f9e by Jeremy Bennett

### Fixes to tutorial after presentation at OSHUG/OSSG workshop.

parent 5fe9fa5e
 ... @@ -74,8 +74,8 @@ assign y3 = {a,2{1'b1}}; ... @@ -74,8 +74,8 @@ assign y3 = {a,2{1'b1}}; ```verilog ```verilog // a a >> 2 a >>> 2 a << 2 a << 3 // a a >> 2 a >>> 2 a << 2 a << 3 // 01001111 00010011 00010011 00111100 00111100 // 01001111 00010011 00010011 00111100 01111000 // 11001111 00110011 11110011 00111100 00111100 // 11001111 00110011 11110011 00111100 01111000 assign y2 = a2 >> 1; // Logical 0's shifted in assign y2 = a2 >> 1; // Logical 0's shifted in assign y2 = a2 >>> 1; // Arithemtic MSB sign bit shifted in assign y2 = a2 >>> 1; // Arithemtic MSB sign bit shifted in assign y2 = a2 << 1; // Logical shift left same result as assign y2 = a2 << 1; // Logical shift left same result as ... @@ -87,12 +87,12 @@ assign y2 = a2 <<< 1; // Arithmetic shift left ... @@ -87,12 +87,12 @@ assign y2 = a2 <<< 1; // Arithmetic shift left ### Rotate right 1 bit ### Rotate right 1 bit ```verilog ```verilog assign y3 = {y3[0],y3[2:1]}; assign y3r = {y3[0],y3[2:1]}; ``` ``` ### Rotate right 2 bit ### Rotate right 2 bit ```verilog ```verilog assign y3 = {y3[1:0],y3[2]}; assign y3r = {y3[1:0],y3[2]}; ``` ``` ## Operator precedence ## Operator precedence ... @@ -221,21 +221,22 @@ en a1 a2 y ... @@ -221,21 +221,22 @@ en a1 a2 y ```verilog ```verilog module pri_encoder module pri_encoder ( ( input wire [4:1] r, input wire [3:0] r, output wire [2:0] y output wire en output wire [1:0] y ) ) always @* always @* if(r[4]) if(r[3]) y = 3'b000; {en,y} = 3'b111; else if(r[3]) y = 3'b011; else if(r[2]) else if(r[2]) y = 3'b010; {en,y} = 3'b110; else if(r[1]) else if(r[1]) y = 3'b001; {en,y} = 3'b101; else if(r[0]) {en,y} = 3'b100; else else y = 3'b000; {en,y} = 3'b000; endmodule endmodule ``` ``` ... ...
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