1. 25 Jun, 2018 1 commit
  2. 17 Jun, 2018 4 commits
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      Integrated ao68000 in Retro-uC · 58a25742
      Fatsie authored
       * Added Retro_uC_m68k subblock
       * Which cores to include is now configurable by a parameter
       * Switched to modelsim for cocotb simulation. vhdlpp of Icarus
         currently fails on the procedure implemented in the c4m package
       * Changed top cell for cocotb simulation of Retro_uC_top from VHDL
         to Verilog. This avoids warning of unsupported VHPI features.
         Due to this switch now the right capitalization has to be used
         for the top level ports.
       * .vcd generation from simulation is now enabled in initial statement
         in the top cell
       * The Retro-uC with the three cores does not fit in the FPGA of the
         XLR8. Now three versions of the files are; one with T80&T65, one with
         M68K&T65 and one with M68K&T80. Each of the version is defined as a
         revision in the quartus project.
       * A fourth revision 'BlinkLed' is also added that only contains a file
         that just blinks LED 13 for debugging purposes.
       * The ao68000 uses ROM for storage of microcode. This result in the
         generation of RAM initialization for the XLR8 FPGA. This is not
         compatible with dual configuration storage on the FPGA. This means
         that when a bitstream containing this core is stored in the Flash of
         the FPGA it will overwrite the XLR8 backup bitstream and you won't be
         able to revert the XLR8 to stock image by shorting the relevant
         resistor. Handle thus with care.
       * Update the compile and svf generation scripts for the XLR8 demo.
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      setleds.c: Use volatile to access memory mapped I/O · 77b95983
      Fatsie authored
      If volatile is not present compiler may optimize accesses away.
  3. 16 Jun, 2018 1 commit
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      WBBus: Fixes for endianness, wishbone block read; implement Sel for IO read/write · 47bf8fd2
      Fatsie authored
       * For endianness now first 8 bits of 32 word in 32bit busmode at address
         A corresponds with address 4*A in 8 bit mode. Updated svf generation
       * Wishbone block read was not taking right address to read from.
       * The Sel WB signal was ignored and is now implemented. Refactored code
         to make is more clean.
  4. 15 Jun, 2018 1 commit
  5. 13 May, 2018 2 commits
  6. 15 Apr, 2018 17 commits
  7. 19 Mar, 2018 2 commits
  8. 27 Feb, 2018 2 commits
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      Renamed block Retro_uC_JTAG to Retro_uC_Control and JTAG command to enable/disable cores · 9f855f76
      Fatsie authored
       * Block was renamed as it does more than handling of JTAG.
       * Initialization of memory after reset depending on enabled core moved
         to Retro_uC_Control
       * Added JTAG command to enable/disable cores through JTAG interface
       * On XLR8 use A0 and A1 as init values for enabling T80/T65
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      Several fixes to get memory access through JTAG functional and more efficient · 111fdefe
      Fatsie authored
       * Arbiter adds wait state before and after the JTAG memory cycle
       * Wishbone interface of JTAG now runs on Clock not TCK
       * Neither T65 or T80 wait for ack to start new cycle.
       * T65 & T80 cpu is run on inverted clock to avoid need of wait state during read.
         This way address is update on falling clock edge, read data generated
         on rising edge and available for CPU on falling edge.
       * WBBus output the T65 Vector data after the clock cycle.
       * In JTAG_RAM cocotb sim write JTAG data not to address 0 as there code is
         located for the CPUs.
  9. 11 Feb, 2018 1 commit
  10. 10 Feb, 2018 3 commits
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      Re-implemented JTAG memory commands: · 78a85f26
      Fatsie authored
       * Put all JTAG handling in separate Retro_uC_JTAG block
       * Extended arbiter to also handle the JTAG WB bus, the JTAG bus gets
         priority over the CPU buses.
       * Data will is read/written through JTAG interface in chunks of 32 bit
       * Updated and run Retro_uC_top and JTAG_RAM cocotb testbenches
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      Add T65 core in _Top block · 7f51810d
      Fatsie authored
       * Extend Arbiter with wb interface for T65, keep non-selected core in reset state
       * Instantiate T65 in top block
       * Add test in top testbench for T80 and T65
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      In WBBus handle the T65 reset vector · e7b17dee
      Fatsie authored
  11. 08 Feb, 2018 2 commits
  12. 31 Jan, 2018 4 commits