Commit fdf66b54 authored by Fatsie's avatar Fatsie

Clean-up & typos

parent cfdf5736
......@@ -23,6 +23,7 @@ entity Retro_uC_top is
TDI: in std_logic;
TDO: out std_logic;
-- GPIO
IO_IN: in std_logic_vector(IOS-1 downto 0);
IO_OUT: out std_logic_vector(IOS-1 downto 0);
IO_EN: out std_logic_vector(IOS-1 downto 0)
......@@ -35,7 +36,6 @@ architecture rtl of Retro_uC_top is
signal CORE_EN: std_logic_vector(IOS-1 downto 0);
-- T80 signals
signal T80_RESET_N: std_logic;
signal T80_Clock: std_logic;
signal T80_WB_Adr: std_logic_vector(15 downto 0);
signal T80_WB_Dat_To: std_logic_vector(7 downto 0);
......@@ -47,7 +47,6 @@ architecture rtl of Retro_uC_top is
signal T80_WB_Err: std_logic;
-- T65 signals
signal T65_RESET_N: std_logic;
signal T65_Clock: std_logic;
signal T65_WB_Adr: std_logic_vector(15 downto 0);
signal T65_WB_Dat_To: std_logic_vector(7 downto 0);
......
......@@ -65,7 +65,7 @@ entity Retro_uC_WBBus is
-- downto 0 in 32 bit mode. In 32 bit WB_Sel_i(0) correspond with bit
-- 7 downt 0.
IOs_Out: out std_logic_vector(IOS-1 downto 0);
-- If possible should be put in high impedance state is not enabled.
-- If possible should be put in high impedance state if not enabled.
-- If not possible it should be documented by the implementation.
IOs_En: out std_logic_vector(IOS-1 downto 0);
IOs_In: in std_logic_vector(IOS-1 downto 0)
......@@ -373,12 +373,14 @@ begin
--------------
T65Vec: process (Clock)
begin
if Rising_Edge(Clock) and cycle = T65_Vector then
case WB_Adr_i(7 downto 0) is
when x"FC" => t65_data_o <= T65_Reset_Vector(7 downto 0);
when x"FD" => t65_data_o <= T65_Reset_Vector(15 downto 8);
when others => t65_data_o <= "XXXXXXXX";
end case;
if Rising_Edge(Clock) then
if cycle = T65_Vector then
case WB_Adr_i(7 downto 0) is
when x"FC" => t65_data_o <= T65_Reset_Vector(7 downto 0);
when x"FD" => t65_data_o <= T65_Reset_Vector(15 downto 8);
when others => t65_data_o <= "XXXXXXXX";
end case;
end if;
end if;
end process;
end architecture;
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