Commit cf63d8b9 authored by Fatsie's avatar Fatsie

Added XLR8 files

parent e5578292
*~
*.pyc
sim_build
boards/XLR8/quartus/db
boards/XLR8/quartus/incremental_db
boards/XLR8/quartus/output_files
boards/XLR8/quartus/simulation
*.rpd
*.pof
*.map
......@@ -10,3 +10,6 @@
[submodule "tools/cocotb"]
path = tools/cocotb
url = https://github.com/potentialventures/cocotb.git
[submodule "rtl/submodules/general-cores"]
path = rtl/submodules/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<output_filename>XLR8Build/extras/quartus/output_files/openxlr8.pof</output_filename>
<n_pages>2</n_pages>
<width>1</width>
<mode>14</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>output_files/Retro-uC.sof<compress_bitstream>1</compress_bitstream></sof_filename>
</bit0>
</sof_data>
<sof_data>
<user_name>Page_1</user_name>
<page_flags>2</page_flags>
<bit0>
<sof_filename>output_files/Retro-uC.sof<compress_bitstream>1</compress_bitstream></sof_filename>
</bit0>
</sof_data>
<version>10</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
<auto_create_rpd>1</auto_create_rpd>
<rpd_little_endian>1</rpd_little_endian>
<options>
<map_file>1</map_file>
</options>
<MAX10_device_options>
<por>0</por>
<io_pullup>1</io_pullup>
<config_from_cfm0_only>0</config_from_cfm0_only>
<isp_source>0</isp_source>
<verify_protect>1</verify_protect>
<epof>0</epof>
<ufm_source>2</ufm_source>
<ufm_filepath>optiboot_xlr8.hex</ufm_filepath>
</MAX10_device_options>
<advanced_options>
<ignore_epcs_id_check>2</ignore_epcs_id_check>
<ignore_condone_check>2</ignore_condone_check>
<plc_adjustment>0</plc_adjustment>
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
<bitslice_pre_padding>1</bitslice_pre_padding>
</advanced_options>
</cof>
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Lite Edition
# Date created = 21:00:28 April 18, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "21:00:28 April 18, 2017"
# Revisions
PROJECT_REVISION = "Retro-uC"
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{ "" "" "" "*" { } { } 0 18236 "" 0 0 "Design Software" 0 -1 0 ""}
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Created on:Sunday, April 16, 2017
Based on:xlr8_top
In this directory the bitstream file will be generated.
You have to follow the XLR8 instruction for generating using
boards/XLR8/quartus/Retro-uC.cof for conversion.
directory boards/XLR8/quartus/XLR8Build has to be linked to ~/Arduino/libraries/XLR8Build
(or other place where you put the Arduino dir).
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element dual_boot_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M08SAU169C8G" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="avalon" internal="dual_boot_0.avalon" type="avalon" dir="end">
<port name="avmm_rcv_address" internal="avmm_rcv_address" />
<port name="avmm_rcv_read" internal="avmm_rcv_read" />
<port name="avmm_rcv_writedata" internal="avmm_rcv_writedata" />
<port name="avmm_rcv_write" internal="avmm_rcv_write" />
<port name="avmm_rcv_readdata" internal="avmm_rcv_readdata" />
</interface>
<interface name="clk" internal="dual_boot_0.clk" type="clock" dir="end">
<port name="clk" internal="clk" />
</interface>
<interface name="nreset" internal="dual_boot_0.nreset" type="reset" dir="end">
<port name="nreset" internal="nreset" />
</interface>
<module
name="dual_boot_0"
kind="altera_dual_boot"
version="16.1"
enabled="1"
autoexport="1">
<parameter name="CLOCK_FREQUENCY" value="16.0" />
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 352 248)
(text "altera_dual_conf" (rect 127 -1 193 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 232 20 244)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "avmm_rcv_address[2..0]" (rect 0 0 105 12)(font "Arial" (font_size 8)))
(text "avmm_rcv_address[2..0]" (rect 4 61 136 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 144 72)(line_width 3))
)
(port
(pt 0 88)
(input)
(text "avmm_rcv_read" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "avmm_rcv_read" (rect 4 77 82 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 144 88)(line_width 1))
)
(port
(pt 0 104)
(input)
(text "avmm_rcv_writedata[31..0]" (rect 0 0 110 12)(font "Arial" (font_size 8)))
(text "avmm_rcv_writedata[31..0]" (rect 4 93 154 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 144 104)(line_width 3))
)
(port
(pt 0 120)
(input)
(text "avmm_rcv_write" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "avmm_rcv_write" (rect 4 109 88 120)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 144 120)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "clk" (rect 4 165 22 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 144 176)(line_width 1))
)
(port
(pt 0 216)
(input)
(text "nreset" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "nreset" (rect 4 205 40 216)(font "Arial" (font_size 8)))
(line (pt 0 216)(pt 144 216)(line_width 1))
)
(port
(pt 0 136)
(output)
(text "avmm_rcv_readdata[31..0]" (rect 0 0 110 12)(font "Arial" (font_size 8)))
(text "avmm_rcv_readdata[31..0]" (rect 4 125 148 136)(font "Arial" (font_size 8)))
(line (pt 0 136)(pt 144 136)(line_width 3))
)
(drawing
(text "avalon" (rect 108 43 252 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "address" (rect 149 67 340 144)(font "Arial" (color 0 0 0)))
(text "read" (rect 149 83 322 176)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 149 99 352 208)(font "Arial" (color 0 0 0)))
(text "write" (rect 149 115 328 240)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 149 131 346 272)(font "Arial" (color 0 0 0)))
(text "clk" (rect 129 147 276 307)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 149 171 316 352)(font "Arial" (color 0 0 0)))
(text "nreset" (rect 108 187 252 387)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 149 211 340 432)(font "Arial" (color 0 0 0)))
(text " altera_dual_conf " (rect 277 232 662 474)(font "Arial" ))
(line (pt 144 32)(pt 208 32)(line_width 1))
(line (pt 208 32)(pt 208 232)(line_width 1))
(line (pt 144 232)(pt 208 232)(line_width 1))
(line (pt 144 32)(pt 144 232)(line_width 1))
(line (pt 145 52)(pt 145 140)(line_width 1))
(line (pt 146 52)(pt 146 140)(line_width 1))
(line (pt 145 156)(pt 145 180)(line_width 1))
(line (pt 146 156)(pt 146 180)(line_width 1))
(line (pt 145 196)(pt 145 220)(line_width 1))
(line (pt 146 196)(pt 146 220)(line_width 1))
(line (pt 0 0)(pt 352 0)(line_width 1))
(line (pt 352 0)(pt 352 248)(line_width 1))
(line (pt 0 248)(pt 352 248)(line_width 1))
(line (pt 0 0)(pt 0 248)(line_width 1))
)
)
component altera_dual_conf is
port (
avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
avmm_rcv_read : in std_logic := 'X'; -- read
avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_rcv_write : in std_logic := 'X'; -- write
avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
nreset : in std_logic := 'X' -- reset_n
);
end component altera_dual_conf;
# system info altera_dual_conf on 2017.06.28.22:55:04
system_info:
name,value
DEVICE,10M08SAU169C8G
DEVICE_FAMILY,MAX 10
GENERATION_ID,1498683304
#
#
# Files generated for altera_dual_conf on 2017.06.28.22:55:04
files:
filepath,kind,attributes,module,is_top
simulation/altera_dual_conf.vhd,VHDL,,altera_dual_conf,true
simulation/submodules/mentor/altera_dual_boot.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_dual_boot,false
simulation/submodules/mentor/alt_dual_boot_avmm.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_dual_boot,false
simulation/submodules/mentor/alt_dual_boot.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,altera_dual_boot,false
simulation/submodules/aldec/altera_dual_boot.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_dual_boot,false
simulation/submodules/aldec/alt_dual_boot_avmm.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_dual_boot,false
simulation/submodules/aldec/alt_dual_boot.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,altera_dual_boot,false
simulation/submodules/cadence/altera_dual_boot.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_dual_boot,false
simulation/submodules/cadence/alt_dual_boot_avmm.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_dual_boot,false
simulation/submodules/cadence/alt_dual_boot.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,altera_dual_boot,false
simulation/submodules/synopsys/altera_dual_boot.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_dual_boot,false
simulation/submodules/synopsys/alt_dual_boot_avmm.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_dual_boot,false
simulation/submodules/synopsys/alt_dual_boot.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,altera_dual_boot,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
altera_dual_conf.dual_boot_0,altera_dual_boot
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for altera_dual_conf</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
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table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
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</head>
<body>
<table class="topTitle">
<tr>
<td class="l">altera_dual_conf</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2017.06.28.22:55:15</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/>All Components
<br/>&#160;&#160;
<a href="#module_dual_boot_0"><b>dual_boot_0</b>
</a> altera_dual_boot 16.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_dual_boot_0"><b>dual_boot_0</b>
</a>
</td>
</tr>
<tr>
<td class="slaveb">avalon&#160;</td>
</tr>
</table>
<a name="module_dual_boot_0"> </a>
<div>
<hr/>
<h2>dual_boot_0</h2>altera_dual_boot v16.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">INTENDED_DEVICE_FAMILY</td>
<td class="parametervalue">MAX10FPGA</td>
</tr>
<tr>
<td class="parametername">CLOCK_FREQUENCY</td>
<td class="parametervalue">16.0</td>
</tr>
<tr>
<td class="parametername">CONFIG_CYCLE</td>
<td class="parametervalue">6</td>
</tr>
<tr>
<td class="parametername">RESET_TIMER_CYCLE</td>
<td class="parametervalue">9</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
</tr>
</table>
</body>
</html>
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="dual_boot_0"
megafunction_name="ALTERA_DUAL_BOOT"
intended_family="MAX 10"
specifies="all_ports">
<global>
<pin name="clk" direction="input" scope="external" />
<pin name="nreset" direction="input" scope="external" />
<pin name="avmm_rcv_address[2..0]" direction="input" scope="external" />
<pin name="avmm_rcv_read" direction="input" scope="external" />
<pin name="avmm_rcv_writedata[31..0]" direction="input" scope="external" />
<pin name="avmm_rcv_write" direction="input" scope="external" />
<pin name="avmm_rcv_readdata[31..0]" direction="output" scope="external" />
</global>
</pinplan>
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="simulation/submodules/mentor/altera_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="modelsim" />
<file
path="simulation/submodules/mentor/alt_dual_boot_avmm.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="modelsim" />
<file
path="simulation/submodules/mentor/alt_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="modelsim" />
<file
path="simulation/submodules/aldec/altera_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="riviera" />
<file
path="simulation/submodules/aldec/alt_dual_boot_avmm.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="riviera" />
<file
path="simulation/submodules/aldec/alt_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="riviera" />
<file
path="simulation/submodules/cadence/altera_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="ncsim" />
<file
path="simulation/submodules/cadence/alt_dual_boot_avmm.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="ncsim" />
<file
path="simulation/submodules/cadence/alt_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="ncsim" />
<file
path="simulation/submodules/synopsys/altera_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="vcs" />
<file
path="simulation/submodules/synopsys/alt_dual_boot_avmm.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="vcs" />
<file
path="simulation/submodules/synopsys/alt_dual_boot.v"
type="VERILOG_ENCRYPT"
library="dual_boot_0"
simulator="vcs" />
<file path="simulation/altera_dual_conf.vhd" type="VHDL" />
<topLevel name="altera_dual_conf" />
<deviceFamily name="max10" />
</simPackage>
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2017.06.28.22:55:15"
outputDirectory="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="MAX 10"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="10M08SAU169C8G"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="8"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<interface name="avalon" kind="avalon" start="0">
<property name="addressAlignment" value="DYNAMIC" />
<property name="addressGroup" value="0" />
<property name="addressSpan" value="32" />
<property name="addressUnits" value="WORDS" />
<property name="alwaysBurstMaxBurst" value="false" />
<property name="associatedClock" value="clk" />
<property name="associatedReset" value="nreset" />
<property name="bitsPerSymbol" value="8" />
<property name="bridgedAddressOffset" value="0" />
<property name="bridgesToMaster" value="" />
<property name="burstOnBurstBoundariesOnly" value="false" />
<property name="burstcountUnits" value="WORDS" />
<property name="constantBurstBehavior" value="false" />
<property name="explicitAddressSpan" value="0" />
<property name="holdTime" value="0" />
<property name="interleaveBursts" value="false" />
<property name="isBigEndian" value="false" />
<property name="isFlash" value="false" />
<property name="isMemoryDevice" value="false" />
<property name="isNonVolatileStorage" value="false" />
<property name="linewrapBursts" value="false" />
<property name="maximumPendingReadTransactions" value="0" />
<property name="maximumPendingWriteTransactions" value="0" />
<property name="minimumUninterruptedRunLength" value="1" />
<property name="printableDevice" value="false" />
<property name="readLatency" value="0" />
<property name="readWaitStates" value="1" />
<property name="readWaitTime" value="1" />
<property name="registerIncomingSignals" value="false" />
<property name="registerOutgoingSignals" value="false" />
<property name="setupTime" value="0" />
<property name="timingUnits" value="Cycles" />
<property name="transparentBridge" value="false" />
<property name="wellBehavedWaitrequest" value="false" />
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<property name="writeWaitStates" value="0" />
<property name="writeWaitTime" value="0" />
<port name="avmm_rcv_address" direction="input" role="address" width="3" />
<port name="avmm_rcv_read" direction="input" role="read" width="1" />
<port
name="avmm_rcv_writedata"
direction="input"
role="writedata"
width="32" />
<port name="avmm_rcv_write" direction="input" role="write" width="1" />
<port
name="avmm_rcv_readdata"
direction="output"
role="readda