Commit b2fda9dd authored by Fatsie's avatar Fatsie

boards/XLR8: Update to Quartus 17.1.0 Lite

parent 2b839033
......@@ -23,3 +23,5 @@ synthesis
layout
Gerber*
boards/cloudv/rtl/verilog/Retro_uC_CloudV.ys
*.qws
.qsys_edit
......@@ -8,7 +8,7 @@ set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH XLR8_tb -section_id eda_simulation
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name DEVICE 10M08SAU169C8G
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
......
......@@ -6,7 +6,7 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element dual_boot_0
......@@ -31,7 +31,7 @@
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="projectName" value="Retro-uC.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
......@@ -54,7 +54,7 @@
<module
name="dual_boot_0"
kind="altera_dual_boot"
version="16.1"
version="17.1"
enabled="1"
autoexport="1">
<parameter name="CLOCK_FREQUENCY" value="16.0" />
......
......@@ -12,12 +12,11 @@ functions, and any output files from any of the foregoing
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
......
......@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2017.06.28.22:55:15</td>
<td class="l">2018.03.11.00:50:46</td>
<td class="r">Datasheet</td>
</tr>
</table>
......@@ -85,7 +85,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<br/>All Components
<br/>&#160;&#160;
<a href="#module_dual_boot_0"><b>dual_boot_0</b>
</a> altera_dual_boot 16.1</span>
</a> altera_dual_boot 17.1</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
......@@ -107,7 +107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_dual_boot_0"> </a>
<div>
<hr/>
<h2>dual_boot_0</h2>altera_dual_boot v16.1
<h2>dual_boot_0</h2>altera_dual_boot v17.1
<br/>
<br/>
<br/>
......@@ -153,8 +153,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.04 seconds</td>
</tr>
</table>
</body>
......
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2017.06.28.22:55:15"
outputDirectory="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/">
date="2018.03.11.00:50:47"
outputDirectory="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
......@@ -117,13 +117,13 @@
</perimeter>
<entity
path=""
parameterizationKey="altera_dual_conf:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SAU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1498683315,AUTO_UNIQUE_ID=(altera_dual_boot:16.1:CLOCK_FREQUENCY=16.0,CONFIG_CYCLE=6,INTENDED_DEVICE_FAMILY=MAX 10,RESET_TIMER_CYCLE=9)"
parameterizationKey="altera_dual_conf:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=10M08SAU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1520725846,AUTO_UNIQUE_ID=(altera_dual_boot:17.1:CLOCK_FREQUENCY=16.0,CONFIG_CYCLE=6,INTENDED_DEVICE_FAMILY=MAX 10,RESET_TIMER_CYCLE=9)"
instancePathKey="altera_dual_conf"
kind="altera_dual_conf"
version="1.0"
name="altera_dual_conf">
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="1498683315" />
<parameter name="AUTO_GENERATION_ID" value="1520725846" />
<parameter name="AUTO_DEVICE" value="10M08SAU169C8G" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
......@@ -132,30 +132,30 @@
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<generatedFiles>
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/altera_dual_conf.vhd"
type="VHDL" />
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/altera_dual_conf.v"
type="VERILOG" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/altera_dual_boot.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/altera_dual_boot.v"
type="VERILOG"
attributes="" />
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot_avmm.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot_avmm.v"
type="VERILOG"
attributes="" />
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot.v"
type="VERILOG"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys" />
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf.qsys" />
</sourceFiles>
<childSourceFiles>
<file
path="/home/verhaegs/software/no-stow/intelFPGA_lite/16.1/ip/altera/altera_dual_boot/altera_dual_boot/altera_dual_boot_hw.tcl" />
path="/home/verhaegs/software/no-stow/intelFPGA_lite/17.1/ip/altera/altera_dual_boot/altera_dual_boot/altera_dual_boot_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Debug" culprit="altera_dual_conf">queue size: 0 starting:altera_dual_conf "altera_dual_conf"</message>
......@@ -179,10 +179,10 @@
</entity>
<entity
path="submodules/"
parameterizationKey="altera_dual_boot:16.1:CLOCK_FREQUENCY=16.0,CONFIG_CYCLE=6,INTENDED_DEVICE_FAMILY=MAX 10,RESET_TIMER_CYCLE=9"
parameterizationKey="altera_dual_boot:17.1:CLOCK_FREQUENCY=16.0,CONFIG_CYCLE=6,INTENDED_DEVICE_FAMILY=MAX 10,RESET_TIMER_CYCLE=9"
instancePathKey="altera_dual_conf:.:dual_boot_0"
kind="altera_dual_boot"
version="16.1"
version="17.1"
name="altera_dual_boot">
<parameter name="CLOCK_FREQUENCY" value="16.0" />
<parameter name="CONFIG_CYCLE" value="6" />
......@@ -190,22 +190,22 @@
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
<generatedFiles>
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/altera_dual_boot.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/altera_dual_boot.v"
type="VERILOG"
attributes="" />
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot_avmm.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot_avmm.v"
type="VERILOG"
attributes="" />
<file
path="/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot.v"
path="/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis/submodules/rtl/alt_dual_boot.v"
type="VERILOG"
attributes="" />
</generatedFiles>
<childGeneratedFiles/>
<sourceFiles>
<file
path="/home/verhaegs/software/no-stow/intelFPGA_lite/16.1/ip/altera/altera_dual_boot/altera_dual_boot/altera_dual_boot_hw.tcl" />
path="/home/verhaegs/software/no-stow/intelFPGA_lite/17.1/ip/altera/altera_dual_boot/altera_dual_boot/altera_dual_boot_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="altera_dual_conf" as="dual_boot_0" />
......
module altera_dual_conf (
clk,
nreset,
avmm_rcv_address,
avmm_rcv_read,
avmm_rcv_writedata,
avmm_rcv_write,
avmm_rcv_readdata);
avmm_rcv_readdata,
clk,
nreset);
input clk;
input nreset;
input [2:0] avmm_rcv_address;
input avmm_rcv_read;
input [31:0] avmm_rcv_writedata;
input avmm_rcv_write;
output [31:0] avmm_rcv_readdata;
input clk;
input nreset;
endmodule
Info: Starting: Create simulation model
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
Progress: Reading input file
Progress: Adding dual_boot_0 [altera_dual_boot 16.1]
Progress: Parameterizing module dual_boot_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: altera_dual_conf: Generating altera_dual_conf "altera_dual_conf" for SIM_VHDL
Info: dual_boot_0: "altera_dual_conf" instantiated altera_dual_boot "dual_boot_0"
Info: altera_dual_conf: Done "altera_dual_conf" with 2 modules, 13 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/altera_dual_conf.spd --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/altera_dual_conf.spd --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: synopsys/vcsmx/synopsys_sim.setup
Info: synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: cadence/cds.lib
Info: cadence/hdl.var
Info: cadence/ncsim_setup.sh
Info: 1 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --block-symbol-file --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf --family="MAX 10" --part=10M08SAU169C8G
Info: qsys-generate /home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf.qsys --block-symbol-file --output-directory=/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
Progress: Reading input file
Progress: Adding dual_boot_0 [altera_dual_boot 16.1]
Progress: Adding dual_boot_0 [altera_dual_boot 17.1]
Progress: Parameterizing module dual_boot_0
Progress: Building connections
Progress: Parameterizing connections
......@@ -46,10 +12,10 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --synthesis=VHDL --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis --family="MAX 10" --part=10M08SAU169C8G
Info: qsys-generate /home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf.qsys --synthesis=VERILOG --output-directory=/home/verhaegs/eda/Chips4Makers/Retro-uC/boards/XLR8/quartus/altera_dual_conf/synthesis --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
Progress: Reading input file
Progress: Adding dual_boot_0 [altera_dual_boot 16.1]
Progress: Adding dual_boot_0 [altera_dual_boot 17.1]
Progress: Parameterizing module dual_boot_0
Progress: Building connections
Progress: Parameterizing connections
......
Info: Starting: Create simulation model
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
Progress: Reading input file
Progress: Adding dual_boot_0 [altera_dual_boot 16.1]
Progress: Parameterizing module dual_boot_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: altera_dual_conf: Generating altera_dual_conf "altera_dual_conf" for SIM_VHDL
Info: dual_boot_0: "altera_dual_conf" instantiated altera_dual_boot "dual_boot_0"
Info: altera_dual_conf: Done "altera_dual_conf" with 2 modules, 13 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/altera_dual_conf.spd --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/altera_dual_conf.spd --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: synopsys/vcsmx/synopsys_sim.setup
Info: synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: cadence/cds.lib
Info: cadence/hdl.var
Info: cadence/ncsim_setup.sh
Info: 1 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/ directory:
Info: aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --block-symbol-file --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
......@@ -12,7 +46,7 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --synthesis=VERILOG --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis --family="MAX 10" --part=10M08SAU169C8G
Info: qsys-generate /home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf.qsys --synthesis=VHDL --output-directory=/home/verhaegs/eda/XLR8/Z80_Arduino/extras/quartus/altera_dual_conf/synthesis --family="MAX 10" --part=10M08SAU169C8G
Progress: Loading quartus/altera_dual_conf.qsys
Progress: Reading input file
Progress: Adding dual_boot_0 [altera_dual_boot 16.1]
......
altera_dual_conf u0 (
.clk (<connected-to-clk>), // clk.clk
.nreset (<connected-to-nreset>), // nreset.reset_n
.avmm_rcv_address (<connected-to-avmm_rcv_address>), // avalon.address
.avmm_rcv_read (<connected-to-avmm_rcv_read>), // .read
.avmm_rcv_writedata (<connected-to-avmm_rcv_writedata>), // .writedata
.avmm_rcv_write (<connected-to-avmm_rcv_write>), // .write
.avmm_rcv_readdata (<connected-to-avmm_rcv_readdata>) // .readdata
.avmm_rcv_readdata (<connected-to-avmm_rcv_readdata>), // .readdata
.clk (<connected-to-clk>), // clk.clk
.nreset (<connected-to-nreset>) // nreset.reset_n
);
component altera_dual_conf is
port (
clk : in std_logic := 'X'; -- clk
nreset : in std_logic := 'X'; -- reset_n
avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
avmm_rcv_read : in std_logic := 'X'; -- read
avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_rcv_write : in std_logic := 'X'; -- write
avmm_rcv_readdata : out std_logic_vector(31 downto 0) -- readdata
avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
nreset : in std_logic := 'X' -- reset_n
);
end component altera_dual_conf;
u0 : component altera_dual_conf
port map (
clk => CONNECTED_TO_clk, -- clk.clk
nreset => CONNECTED_TO_nreset, -- nreset.reset_n
avmm_rcv_address => CONNECTED_TO_avmm_rcv_address, -- avalon.address
avmm_rcv_read => CONNECTED_TO_avmm_rcv_read, -- .read
avmm_rcv_writedata => CONNECTED_TO_avmm_rcv_writedata, -- .writedata
avmm_rcv_write => CONNECTED_TO_avmm_rcv_write, -- .write
avmm_rcv_readdata => CONNECTED_TO_avmm_rcv_readdata -- .readdata
avmm_rcv_readdata => CONNECTED_TO_avmm_rcv_readdata, -- .readdata
clk => CONNECTED_TO_clk, -- clk.clk
nreset => CONNECTED_TO_nreset -- nreset.reset_n
);
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="altera_dual_conf" kind="system" version="16.1" fabric="QSYS">
<!-- Format version 16.1 203 (Future versions may contain additional information.) -->
<!-- 2017.06.28.22:55:15 -->
<EnsembleReport name="altera_dual_conf" kind="system" version="17.1" fabric="QSYS">
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
<!-- 2018.03.11.00:50:47 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
......@@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1498683315</value>
<value>1520725846</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -101,7 +101,7 @@
</parameter>
<parameter name="projectName">
<type>java.lang.String</type>
<value></value>
<value>Retro-uC.qpf</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -150,7 +150,7 @@
<module
name="dual_boot_0"
kind="altera_dual_boot"
version="16.1"
version="17.1"
path="dual_boot_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
......@@ -203,7 +203,7 @@ the requested settings for a module instance. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="16.1">
<interface name="clk" kind="clock_sink" version="17.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
......@@ -248,7 +248,7 @@ parameters are a RESULT of the module parameters. -->
<role>clk</role>
</port>
</interface>
<interface name="nreset" kind="reset_sink" version="16.1">
<interface name="nreset" kind="reset_sink" version="17.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
......@@ -293,7 +293,7 @@ parameters are a RESULT of the module parameters. -->
<role>reset_n</role>
</port>
</interface>
<interface name="avalon" kind="avalon_slave" version="16.1">
<interface name="avalon" kind="avalon_slave" version="17.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
......@@ -665,7 +665,7 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Altera Dual Configuration</displayName>
<version>16.1</version>
<version>17.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
......@@ -673,7 +673,7 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Input</displayName>
<version>16.1</version>
<version>17.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
......@@ -681,7 +681,7 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<version>16.1</version>
<version>17.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
......@@ -689,8 +689,8 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<version>16.1</version>
<version>17.1</version>
</plugin>
<reportVersion>16.1 203</reportVersion>
<uniqueIdentifier>FEE21F12522E0000015CF07C9601</uniqueIdentifier>
<reportVersion>17.1 590</reportVersion>
<uniqueIdentifier>0242B5DFE4A6000001621252ED11</uniqueIdentifier>
</EnsembleReport>
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_TOOL_VERSION "16.1"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "altera_dual_conf" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../altera_dual_conf.sopcinfo"]
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name SLD_INFO "QSYS_NAME altera_dual_conf HAS_SOPCINFO 1 GENERATION_ID 1498683315"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name SLD_INFO "QSYS_NAME altera_dual_conf HAS_SOPCINFO 1 GENERATION_ID 1520725846"
set_global_assignment -library "altera_dual_conf" -name MISC_FILE [file join $::quartus(qip_path) "../altera_dual_conf.cmp"]
set_global_assignment -library "altera_dual_conf" -name SLD_FILE [file join $::quartus(qip_path) "altera_dual_conf.debuginfo"]
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
......@@ -15,7 +15,7 @@ set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -na
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTQ5ODY4MzMxNQ==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyMDcyNTg0Ng==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQVUxNjlDOEc=::QXV0byBERVZJQ0U="
set_global_assignment -entity "altera_dual_conf" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
......@@ -27,18 +27,18 @@ set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -na
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_VERSION "MTYuMQ=="
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_VERSION "MTcuMQ=="
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIER1YWwgQ29uZmlndXJhdGlvbiBhbGxvdyBjdXN0b21lcnMgdG8gcGVyZm9ybSBkZXNpZ24gdXBkYXRlLg=="
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "SU5URU5ERURfREVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfRlJFUVVFTkNZ::MTYuMA==::Q2xvY2sgZnJlcXVlbmN5"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "Q09ORklHX0NZQ0xF::Ng==::Q09ORklHX0NZQ0xF"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_COMPONENT_PARAMETER "UkVTRVRfVElNRVJfQ1lDTEU=::OQ==::UkVTRVRfVElNRVJfQ1lDTEU="
set_global_assignment -library "altera_dual_conf" -name VHDL_FILE [file join $::quartus(qip_path) "altera_dual_conf.vhd"]
set_global_assignment -library "altera_dual_conf" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_dual_conf.v"]
set_global_assignment -library "altera_dual_conf" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_dual_boot.v"]
set_global_assignment -library "altera_dual_conf" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/alt_dual_boot_avmm.v"]
set_global_assignment -library "altera_dual_conf" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/rtl/alt_dual_boot.v"]
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_TOOL_NAME "altera_dual_boot"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_TOOL_VERSION "16.1"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_TOOL_VERSION "17.1"
set_global_assignment -entity "altera_dual_boot" -library "altera_dual_conf" -name IP_TOOL_ENV "Qsys"
// altera_dual_conf.v
// Generated using ACDS version 16.1 203
// Generated using ACDS version 17.1 590
`timescale 1 ps / 1 ps
module altera_dual_conf (
......
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
......
......@@ -6,12 +6,11 @@
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
component xlr8_ram
......
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "16.1"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "xlr8_ram.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "xlr8_ram.cmp"]
......@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.1.2 Build 203 01/18/2017 SJ Lite Edition
-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-- ************************************************************
......@@ -26,12 +26,11 @@
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
......@@ -63,14 +62,14 @@ BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "MAX 10",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 13,
......@@ -118,7 +117,7 @@ END SYN;
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
......@@ -128,14 +127,14 @@ END SYN;
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
......
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