Commit 9f855f76 authored by Fatsie's avatar Fatsie

Renamed block Retro_uC_JTAG to Retro_uC_Control and JTAG command to enable/disable cores

 * Block was renamed as it does more than handling of JTAG.
 * Initialization of memory after reset depending on enabled core moved
   to Retro_uC_Control
 * Added JTAG command to enable/disable cores through JTAG interface
 * On XLR8 use A0 and A1 as init values for enabling T80/T65
parent 111fdefe
......@@ -146,6 +146,8 @@ set_global_assignment -name EDA_TEST_BENCH_NAME XLR8_tb -section_id eda_simulati
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id XLR8_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Retro_uC_XLR8_tb -section_id XLR8_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../rtl/vhdl/Retro_uC_XLR8_tb.vhdl -section_id XLR8_tb -hdl_version VHDL_2008
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_tap_fsm.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_tap_controller.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_pkg.vhdl
......@@ -160,9 +162,15 @@ set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80_R
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80s.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/bench/vhdl/ROM80.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t65/rtl/vhdl/T65_Pack.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t65/rtl/vhdl/T65_ALU.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t65/rtl/vhdl/T65_MCode.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t65/rtl/vhdl/T65.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_jtag.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_wbbus.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_arbiter.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_t80.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_t65.vhdl
set_global_assignment -name QIP_FILE xlr8_ram.qip
set_global_assignment -name VHDL_FILE ../rtl/vhdl/Retro_uC_ram.vhdl
set_global_assignment -name QSYS_FILE altera_dual_conf.qsys
......
......@@ -83,9 +83,9 @@ architecture rtl of Retro_uC_XLR8 is
-- 20/21: SCL/SDA
-- other signal not currently handled by JTAG, directly connected
constant IOS: integer := 22;
signal IO_IN: std_logic_vector(IOS-1 downto 0);
signal IO_OUT: std_logic_vector(IOS-1 downto 0);
signal IO_EN: std_logic_vector(IOS-1 downto 0);
signal IO_IN: std_logic_vector(IOS-1 downto 0);
signal IO_OUT: std_logic_vector(IOS-1 downto 0);
signal IO_EN: std_logic_vector(IOS-1 downto 0);
-- External JTAG signals
signal TRST_N: std_logic;
......@@ -185,6 +185,9 @@ begin
Clock => Clock,
RESET_N => RESET_N,
T80_Enable => A0,
T65_Enable => A1,
TRST_N => TRST_N,
TCK => TCK,
TMS => TMS,
......
......@@ -26,7 +26,6 @@ entity Retro_uC_WBArbiter is
Bus_WB_Err: in std_logic;
T80_Enable: in std_logic;
T80_RESET_N: out std_logic;
T80_Clock: out std_logic;
T80_WB_Adr: in std_logic_vector(15 downto 0);
T80_WB_Dat_To: out std_logic_vector(7 downto 0);
......@@ -38,7 +37,6 @@ entity Retro_uC_WBArbiter is
T80_WB_Err: out std_logic;
T65_Enable: in std_logic;
T65_RESET_N: out std_logic;
T65_Clock: out std_logic;
T65_WB_Adr: in std_logic_vector(15 downto 0);
T65_WB_Dat_To: out std_logic_vector(7 downto 0);
......@@ -49,28 +47,20 @@ entity Retro_uC_WBArbiter is
T65_WB_Ack: out std_logic;
T65_WB_Err: out std_logic;
JTAG_WB_Adr: in std_logic_vector(15 downto 0);
JTAG_WB_Dat_To: out std_logic_vector(31 downto 0);
JTAG_WB_Dat_From: in std_logic_vector(31 downto 0);
JTAG_WB_WE: in std_logic;
JTAG_WB_Cyc: in std_logic;
JTAG_WB_Stb: in std_logic;
JTAG_WB_Ack: out std_logic;
JTAG_WB_Err: out std_logic
Ctrl_WB_Adr: in std_logic_vector(15 downto 0);
Ctrl_WB_Dat_To: out std_logic_vector(31 downto 0);
Ctrl_WB_Dat_From: in std_logic_vector(31 downto 0);
Ctrl_WB_WE: in std_logic;
Ctrl_WB_Cyc: in std_logic;
Ctrl_WB_Stb: in std_logic;
Ctrl_WB_Ack: out std_logic;
Ctrl_WB_Err: out std_logic
);
end entity Retro_uC_WBArbiter;
architecture rtl of Retro_uC_WBArbiter is
type INIT_STATE_TYPE is (
Init_Reset,
Init_StartCycle,
Init_EndCycle,
Init_Done
);
signal jtag_cycle: boolean;
signal jtag_cycle_hold: boolean;
signal state: INIT_STATE_TYPE;
begin
-- Currently clock is distributed to all connected CPUs
T80_Clock <= Clock;
......@@ -78,115 +68,33 @@ begin
process (all)
begin
jtag_cycle <= (JTAG_WB_Cyc = '1') and (JTAG_WB_Stb = '1');
jtag_cycle <= (Ctrl_WB_Cyc = '1') and (Ctrl_WB_Stb = '1');
if RESET_N = '0' then
jtag_cycle_hold <= false;
elsif rising_edge(Clock) then
jtag_cycle_hold <= jtag_cycle;
end if;
if RESET_N = '0' then
state <= Init_Reset;
elsif rising_edge(Clock) then
case state is
when Init_Reset =>
if (T65_Enable = '1') or (T80_Enable = '1') then
state <= Init_StartCycle;
else
state <= Init_Done;
end if;
when Init_StartCycle =>
if Bus_WB_Ack = '1' then
state <= Init_EndCycle;
else
state <= Init_StartCycle;
end if;
when Init_EndCycle =>
if Bus_WB_Ack = '0' then
state <= Init_Done;
else
state <= Init_EndCycle;
end if;
when Init_Done =>
state <= Init_Done;
when others =>
state <= Init_Reset;
end case;
end if;
-- Keep the non-selected cores in reset state
if state /= Init_Done then
T80_RESET_N <= '0';
T65_RESET_N <= '0';
elsif T80_Enable = '1' then
T80_RESET_N <= RESET_N;
T65_RESET_N <= '0';
elsif T65_Enable = '1' then
T80_RESET_N <= '0';
T65_RESET_N <= RESET_N;
else
T80_RESET_N <= '0';
T65_RESET_N <= '0';
end if;
-- Do the WB bus multiplexing
-- Priority order: Init, JTAG, T80, T65
-- During init a HALT instruction is written to the memory
if state /= Init_Done then
-- We perform a write operation to address 0
Bus_BusMode <= '1'; -- 32 bit
Bus_WB_Adr <= (others => '0');
if T80_Enable = '1' then
Bus_WB_Dat_To <= x"00000076"; -- HALT
elsif T65_Enable = '1' then
Bus_WB_Dat_To <= x"0000004C"; -- JMP $0000
else
Bus_WB_Dat_To <= x"DEADBEEF";
end if;
if state = Init_StartCycle then
Bus_WB_Cyc <= '1';
Bus_WB_Stb <= '1';
else
Bus_WB_Cyc <= '0';
Bus_WB_Stb <= '0';
end if;
Bus_WB_Sel <= "1111";
Bus_WB_WE <= '1';
JTAG_WB_Dat_To <= (others => 'X');
JTAG_WB_Ack <= '0';
JTAG_WB_Err <= '0';
T80_WB_Dat_To <= (others => 'X');
T80_WB_Ack <= '0';
T80_WB_Err <= '0';
T65_WB_Dat_To <= (others => 'X');
T65_WB_Ack <= '0';
T65_WB_Err <= '0';
elsif jtag_cycle then
-- Priority order: JTAG, T80, T65
if jtag_cycle then
Bus_BusMode <= '1'; -- 32 bit
Bus_WB_Adr <= JTAG_WB_Adr;
Bus_WB_Dat_To <= JTAG_WB_Dat_From;
Bus_WB_Cyc <= JTAG_WB_Cyc;
Bus_WB_Adr <= Ctrl_WB_Adr;
Bus_WB_Dat_To <= Ctrl_WB_Dat_From;
Bus_WB_Cyc <= Ctrl_WB_Cyc;
Bus_WB_Sel <= "1111";
if not jtag_cycle_hold then
-- Insert a wait cycle when switching from other bus to JTAG bus
Bus_WB_Stb <= '0';
else
Bus_WB_Stb <= JTAG_WB_Stb;
Bus_WB_Stb <= Ctrl_WB_Stb;
end if;
Bus_WB_WE <= JTAG_WB_WE;
Bus_WB_WE <= Ctrl_WB_WE;
JTAG_WB_Dat_To <= Bus_WB_Dat_From;
JTAG_WB_Ack <= Bus_WB_Ack;
JTAG_WB_Err <= Bus_WB_Err;
Ctrl_WB_Dat_To <= Bus_WB_Dat_From;
Ctrl_WB_Ack <= Bus_WB_Ack;
Ctrl_WB_Err <= Bus_WB_Err;
T80_WB_Dat_To <= (others => 'X');
T80_WB_Ack <= '0';
......@@ -198,16 +106,16 @@ begin
elsif jtag_cycle_hold then -- Insert wait cycle after JTAG cycle has ended
Bus_BusMode <= '1'; -- 32 bit
Bus_WB_Adr <= JTAG_WB_Adr;
Bus_WB_Dat_To <= JTAG_WB_Dat_From;
Bus_WB_Cyc <= JTAG_WB_Cyc;
Bus_WB_Adr <= Ctrl_WB_Adr;
Bus_WB_Dat_To <= Ctrl_WB_Dat_From;
Bus_WB_Cyc <= Ctrl_WB_Cyc;
Bus_WB_Sel <= "1111";
Bus_WB_Stb <= '0';
Bus_WB_WE <= '0';
JTAG_WB_Dat_To <= Bus_WB_Dat_From;
JTAG_WB_Ack <= Bus_WB_Ack;
JTAG_WB_Err <= Bus_WB_Err;
Ctrl_WB_Dat_To <= Bus_WB_Dat_From;
Ctrl_WB_Ack <= Bus_WB_Ack;
Ctrl_WB_Err <= Bus_WB_Err;
T80_WB_Dat_To <= (others => 'X');
T80_WB_Ack <= '0';
......@@ -227,9 +135,9 @@ begin
Bus_WB_Stb <= T80_WB_Stb;
Bus_WB_WE <= T80_WB_WE;
JTAG_WB_Dat_To <= (others => 'X');
JTAG_WB_Ack <= '0';
JTAG_WB_Err <= '0';
Ctrl_WB_Dat_To <= (others => 'X');
Ctrl_WB_Ack <= '0';
Ctrl_WB_Err <= '0';
T80_WB_Dat_To <= Bus_WB_Dat_From(7 downto 0);
T80_WB_Ack <= Bus_WB_Ack;
......@@ -249,9 +157,9 @@ begin
Bus_WB_Stb <= T65_WB_Stb;
Bus_WB_WE <= T65_WB_WE;
JTAG_WB_Dat_To <= (others => 'X');
JTAG_WB_Ack <= '0';
JTAG_WB_Err <= '0';
Ctrl_WB_Dat_To <= (others => 'X');
Ctrl_WB_Ack <= '0';
Ctrl_WB_Err <= '0';
T80_WB_Dat_To <= (others => 'X');
T80_WB_Ack <= '0';
......@@ -270,9 +178,9 @@ begin
Bus_WB_Stb <= '0';
Bus_WB_WE <= 'X';
JTAG_WB_Dat_To <= (others => 'X');
JTAG_WB_Ack <= '0';
JTAG_WB_Err <= '0';
Ctrl_WB_Dat_To <= (others => 'X');
Ctrl_WB_Ack <= '0';
Ctrl_WB_Err <= '0';
T80_WB_Dat_To <= (others => 'X');
T80_WB_Ack <= '0';
......
-- The Retro_uC JTAG interface.
-- The Retro_uC top control block. It contains a JTAG interface so the control
-- can be configured through this interface.
--
-- Next to the normal boundary scan it will also handle commands sepcific for
-- the Retro_uC like memory access.
......@@ -12,13 +13,14 @@ use ieee.numeric_std.ALL;
use work.c4m_jtag.ALL;
entity Retro_uC_JTAG is
entity Retro_uC_Control is
generic (
IOS: integer := 1024;
VERSION: std_logic_vector(3 downto 0)
);
port (
RESET_N: in std_logic;
Clock: in std_logic; -- Clock for Wishbone bus
-- The TAP signals
......@@ -46,11 +48,27 @@ entity Retro_uC_JTAG is
WB_Stb_o: out std_logic;
WB_Cyc_o: out std_logic;
WB_Ack_i: in std_logic;
WB_Err_i: in std_logic
WB_Err_i: in std_logic;
-- Enabling cores, initialized during reset by the input signals
-- Can be controlled later by JTAG commands
T80_Enable_In: in std_logic;
T80_Enable_Out: out std_logic;
T65_Enable_In: in std_logic;
T65_Enable_Out: out std_logic
);
end Retro_uC_Control;
architecture rtl of Retro_uC_Control is
type INIT_STATE_TYPE is (
Init_Reset,
Init_MemCycle,
Init_Run
);
end Retro_uC_JTAG;
signal Init_State: INIT_STATE_TYPE;
signal ADDR_INIT: std_logic_vector(15 downto 0);
signal DATA_INIT: std_logic_vector(31 downto 0);
architecture rtl of Retro_uC_JTAG is
signal TAP_STATE: TAPSTATE_TYPE;
signal DRSTATE: std_logic;
constant IR_WIDTH: integer := 3;
......@@ -72,8 +90,83 @@ architecture rtl of Retro_uC_JTAG is
signal done_read: boolean;
signal do_write: boolean;
signal done_write: boolean;
signal S_WB_Stb: std_logic;
signal JTAG_Stb: std_logic;
constant CMD_ENABLE: std_logic_vector(IR_WIDTH-1 downto 0) := "100";
signal ISENABLECMD: boolean;
signal do_enable: boolean;
signal done_enable: boolean;
signal T80_Enable: std_logic;
signal T65_Enable: std_logic;
signal Enable_SR: std_logic_vector(1 downto 0);
begin
-- Handle init
Init: process(RESET_N, Clock)
begin
if RESET_N = '0' then
Init_State <= Init_Reset;
elsif rising_edge(Clock) then
if Init_State = Init_Reset then
Init_State <= Init_MemCycle;
elsif Init_State = Init_MemCycle then
if WB_Ack_i = '1' then
Init_State <= Init_Run;
end if;
elsif Init_State /= Init_Run then
Init_State <= Init_Reset;
end if;
end if;
end process;
ADDR_INIT <= x"0000";
DATA_INIT <= x"000000C3" when T80_Enable = '1' else -- JP $0000
x"0000004C" when T65_Enable = '1' else -- JMP $0000
x"XXXXXXXX";
-- Handle enable signals
Enable: process(Clock)
begin
if rising_edge(Clock) then
if RESET_N = '0' then
done_enable <= false;
T80_Enable <= T80_Enable_In;
T65_Enable <= T65_Enable_In;
elsif do_enable then
done_enable <= true;
T80_Enable <= Enable_SR(1);
T65_Enable <= Enable_SR(0);
end if;
if done_enable and not do_enable then
done_enable <= false;
end if;
end if;
end process;
T80_Enable_Out <= T80_Enable when Init_State = Init_Run else '0';
T65_Enable_Out <= T65_Enable when Init_State = Init_Run else '0';
ISENABLECMD <= DRSTATE = '1' and IR = CMD_ENABLE;
process (TCK, TRST_N)
begin
if rising_edge(TCK) then
if ISENABLECMD then
if TAP_STATE = Capture then
Enable_SR(1) <= T80_Enable;
Enable_SR(0) <= T65_Enable;
elsif TAP_STATE = Shift then
Enable_SR(0) <= Enable_SR(1);
Enable_SR(1) <= TDI;
elsif TAP_STATE = Update then
do_enable <= true;
end if;
end if;
if do_enable and done_enable then
do_enable <= false;
end if;
end if;
end process;
TDO <= Enable_SR(0) when ISENABLECMD and TAP_STATE = Shift else
'Z';
-- The TAP controller
JTAG: component c4m_jtag_tap_controller
generic map (
......@@ -104,7 +197,7 @@ begin
-- has to happen after every 32 bits more bits will be lost, less bits will
-- result with old data in memory be partly shifted.
-- For CMD_MEMWR also the data in the location will be read and shifted out.
-- TODO: Allow streaming of longer
-- TODO: Allow streaming of longer length than 32 bits
ISADDRCMD <= DRSTATE = '1' and IR = CMD_MEMADDR;
ISREADCMD <= DRSTATE = '1' and (IR = CMD_MEMRD or IR = CMD_MEMWR);
ISWRITECMD <= DRSTATE = '1' and (IR = CMD_MEMWR);
......@@ -123,7 +216,7 @@ begin
done_read <= false;
do_write <= false;
done_write <= false;
S_WB_Stb <= '0';
JTAG_Stb <= '0';
else
if rising_edge(TCK) then
-- Shift address register
......@@ -168,10 +261,10 @@ begin
if rising_edge(Clock) then
-- Do read or write cycle, do first read cycle
-- TODO: See if we can get rid of extra TCK cycles for handling S_WB_Stb
-- TODO: See if we can get rid of extra TCK cycles for handling JTAG_Stb
if do_read then
if (S_WB_Stb = '0') and not done_read then
S_WB_Stb <= '1';
if (JTAG_Stb = '0') and not done_read then
JTAG_Stb <= '1';
elsif WB_Ack_i = '1' or WB_Err_i = '1' then
done_read <= true;
if WB_Ack_i = '1' then
......@@ -179,33 +272,58 @@ begin
else
DATA_RD <= (others => 'X');
end if;
S_WB_Stb <= '0';
JTAG_Stb <= '0';
end if;
elsif do_write then
if (S_WB_Stb = '0') and not done_write then
S_WB_Stb <= '1';
if (JTAG_Stb = '0') and not done_write then
JTAG_Stb <= '1';
elsif WB_Ack_i = '1' or WB_Err_i = '1' then
done_write <= true;
S_WB_Stb <= '0';
JTAG_Stb <= '0';
end if;
end if;
if done_read and not do_read then
done_read <= false;
end if;
if done_write and not do_write then
done_write <= false;
end if;
end if;
end if;
end process;
WBBUS: process (all)
begin
if Init_State = Init_MemCycle then
WB_Adr_o <= ADDR_INIT;
WB_Dat_o <= DATA_INIT;
WB_WE_o <= '1';
WB_Cyc_o <= '1';
WB_Stb_o <= '1';
else
-- Do read has priority over do_write
if do_read then
WB_Adr_o <= std_logic_vector(ADDR_SR);
else
WB_Adr_o <= std_logic_vector(ADDR_WR);
end if;
if do_write then
WB_Dat_o <= DATA_WR;
else
WB_Dat_o <= (others => 'X');
end if;
if done_read and not do_read then
done_read <= false;
if (not do_read) and do_write then
WB_WE_o <= '1';
else
WB_WE_o <= '0';
end if;
if done_write and not do_write then
done_write <= false;
if do_read or do_write then
WB_Cyc_o <= '1';
else
WB_Cyc_o <= '0';
end if;
WB_Stb_o <= JTAG_Stb;
end if;
end process;
-- Do read has priority over do_write
WB_Adr_o <= std_logic_vector(ADDR_SR) when do_read else
std_logic_vector(ADDR_WR);
WB_Dat_o <= DATA_WR when do_write else
(others => 'X');
WB_WE_o <= '1' when (not do_read) and do_write else
'0';
WB_Cyc_o <= '1' when do_read or do_write else
'0';
WB_Stb_o <= S_WB_Stb;
end rtl;
......@@ -59,14 +59,16 @@ architecture rtl of Retro_uC_top is
signal T65_WB_Err: std_logic;
-- JTAG signals
signal JTAG_WB_Adr: std_logic_vector(15 downto 0);
signal JTAG_WB_Dat_To: std_logic_vector(31 downto 0);
signal JTAG_WB_Dat_From: std_logic_vector(31 downto 0);
signal JTAG_WB_WE: std_logic;
signal JTAG_WB_Stb: std_logic;
signal JTAG_WB_Cyc: std_logic;
signal JTAG_WB_Ack: std_logic;
signal JTAG_WB_Err: std_logic;
signal Ctrl_WB_Adr: std_logic_vector(15 downto 0);
signal Ctrl_WB_Dat_To: std_logic_vector(31 downto 0);
signal Ctrl_WB_Dat_From: std_logic_vector(31 downto 0);
signal Ctrl_WB_WE: std_logic;
signal Ctrl_WB_Stb: std_logic;
signal Ctrl_WB_Cyc: std_logic;
signal Ctrl_WB_Ack: std_logic;
signal Ctrl_WB_Err: std_logic;
signal Ctrl_T80_Enable: std_logic;
signal Ctrl_T65_Enable: std_logic;
-- WBBus signals
signal Bus_BusMode: std_logic;
......@@ -87,7 +89,7 @@ begin
T80Core: entity work.Retro_uC_t80
port map (
Clock => T80_Clock,
RESET_N => T80_RESET_N,
RESET_N => Ctrl_T80_Enable,
WB_Adr_o => T80_WB_Adr,
WB_Dat_o => T80_WB_Dat_From,
WB_Dat_i => T80_WB_Dat_To,
......@@ -100,7 +102,7 @@ begin
T65Core: entity work.Retro_uC_t65
port map (
Clock => T65_Clock,
RESET_N => T65_RESET_N,
RESET_N => Ctrl_T65_Enable,
WB_Adr_o => T65_WB_Adr,
WB_Dat_o => T65_WB_Dat_From,
WB_Dat_i => T65_WB_Dat_To,
......@@ -112,12 +114,13 @@ begin
);
-- The TAP controller
JTAG: entity work.Retro_uC_JTAG
JTAG: entity work.Retro_uC_Control
generic map (
IOS => IOS,
VERSION => "0101"
)
port map (
RESET_N => RESET_N,
Clock => Clock,
TCK => TCK,
TMS => TMS,
......@@ -130,14 +133,18 @@ begin
PAD_IN => IO_IN,
PAD_EN => IO_EN,
PAD_OUT => IO_OUT,
WB_Adr_o => JTAG_WB_Adr,
WB_Dat_o => JTAG_WB_Dat_From,
WB_Dat_i => JTAG_WB_Dat_To,
WB_WE_o => JTAG_WB_WE,
WB_Stb_o => JTAG_WB_Stb,
WB_Cyc_o => JTAG_WB_Cyc,
WB_Ack_i => JTAG_WB_Ack,
WB_Err_i => JTAG_WB_Err
WB_Adr_o => Ctrl_WB_Adr,
WB_Dat_o => Ctrl_WB_Dat_From,
WB_Dat_i => Ctrl_WB_Dat_To,
WB_WE_o => Ctrl_WB_WE,
WB_Stb_o => Ctrl_WB_Stb,
WB_Cyc_o => Ctrl_WB_Cyc,
WB_Ack_i => Ctrl_WB_Ack,
WB_Err_i => Ctrl_WB_Err,
T80_Enable_In => T80_Enable,
T80_Enable_Out => Ctrl_T80_Enable,
T65_Enable_in => T65_Enable,
T65_Enable_Out => Ctrl_T65_Enable
);
-- The Bus
......@@ -181,8 +188,7 @@ begin
Bus_WB_Ack => Bus_WB_Ack,
Bus_WB_Err => Bus_WB_Err,
T80_Enable => T80_Enable,
T80_RESET_N => T80_RESET_N,
T80_Enable => Ctrl_T80_Enable,
T80_Clock => T80_Clock,
T80_WB_Adr => T80_WB_Adr,
T80_WB_Dat_To => T80_WB_Dat_To,
......@@ -193,8 +199,7 @@ begin
T80_WB_Ack => T80_WB_Ack,
T80_WB_Err => T80_WB_Err,
T65_Enable => T65_Enable,
T65_RESET_N => T65_RESET_N,
T65_Enable => Ctrl_T65_Enable,
T65_Clock => T65_Clock,
T65_WB_Adr => T65_WB_Adr,
T65_WB_Dat_To => T65_WB_Dat_To,
......@@ -205,13 +210,13 @@ begin
T65_WB_Ack => T65_WB_Ack,
T65_WB_Err => T65_WB_Err,
JTAG_WB_Adr => JTAG_WB_Adr,
JTAG_WB_Dat_To => JTAG_WB_Dat_To,
JTAG_WB_Dat_From => JTAG_WB_Dat_From,
JTAG_WB_WE => JTAG_WB_WE,
JTAG_WB_Stb => JTAG_WB_Stb,
JTAG_WB_Cyc => JTAG_WB_Cyc,
JTAG_WB_Ack => JTAG_WB_Ack,
JTAG_WB_Err => JTAG_WB_Err
Ctrl_WB_Adr => Ctrl_WB_Adr,
Ctrl_WB_Dat_To => Ctrl_WB_Dat_To,
Ctrl_WB_Dat_From => Ctrl_WB_Dat_From,
Ctrl_WB_WE => Ctrl_WB_WE,
Ctrl_WB_Stb => Ctrl_WB_Stb,
Ctrl_WB_Cyc => Ctrl_WB_Cyc,
Ctrl_WB_Ack => Ctrl_WB_Ack,
Ctrl_WB_Err => Ctrl_WB_Err
);
end rtl;
......@@ -27,7 +27,7 @@ VHDL_SOURCES = \
$(T65VHDLDIR)/T65_MCode.vhd \
$(T65VHDLDIR)/T65.vhd \
$(VHDLDIR)/Retro_uC_ram.vhdl \
$(VHDLDIR)/Retro_uC_jtag.vhdl \
$(VHDLDIR)/Retro_uC_control.vhdl \
$(VHDLDIR)/Retro_uC_wbbus.vhdl \
$(VHDLDIR)/Retro_uC_arbiter.vhdl \
$(VHDLDIR)/Retro_uC_t80.vhdl \
......
......@@ -61,12 +61,13 @@ def test02_mem(dut):
addr = BinaryValue(256, 16)
# Init, enable t65
dut.reset_n = 1
dut.t65_enable = 1
dut.t80_enable = 0
yield Timer(2*clk_period)
dut.reset_n = 1
# MEMADDR => 0
dut._log.info("Setting address to 0")
# MEMADDR => 256
dut._log.info("Setting address to 256")
yield master.load_ir(MEMADDR)
yield master.shift_data(addr)
......@@ -76,8 +77,8 @@ def test02_mem(dut):
yield master.shift_data(data0)
yield master.shift_data(dataFF)
# MEMADDR => 0
dut._log.info("Setting address to 0")
# MEMADDR => 256
dut._log.info("Setting address to 256")
yield master.load_ir(MEMADDR)
yield master.shift_data(addr)
......@@ -96,8 +97,8 @@ def test02_mem(dut):
yield Timer(2*clk_period)
dut.reset_n = 1
# MEMADDR => 0
dut._log.info("Setting address to 0")
# MEMADDR => 256
dut._log.info("Setting address to 256")
yield master.load_ir(MEMADDR)
yield master.shift_data(addr)
......@@ -110,7 +111,7 @@ def test02_mem(dut):
assert(master.result == data10)
# MEMADDR => 0
dut._log.info("Setting address to 0")
dut._log.info("Setting address to 256")
yield master.load_ir(MEMADDR)
yield master.shift_data(addr)
......
......@@ -27,7 +27,7 @@ VHDL_SOURCES = \
$(T65VHDLDIR)/T65_MCode.vhd \
$(T65VHDLDIR)/T65.vhd \
$(VHDLDIR)/Retro_uC_ram.vhdl \
$(VHDLDIR)/Retro_uC_jtag.vhdl \
$(VHDLDIR)/Retro_uC_control.vhdl \
$(VHDLDIR)/Retro_uC_wbbus.vhdl \
$(VHDLDIR)/Retro_uC_arbiter.vhdl \
$(VHDLDIR)/Retro_uC_t80.vhdl \
......
../../../rtl/submodules/c4m_jtag/sim/cocotb/c4m_jtag.py
\ No newline at end of file
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
from cocotb.utils import get_sim_steps
from cocotb.binary import BinaryValue