Commit 6c902932 authored by Fatsie's avatar Fatsie

* Removed XLR8 specific stuff from Retro_uC_top and created Retro_uC_XLR8 top

 * Provide generic RAM block used for simulation
parent d970bb4b
#source ../../../XLR8Core/extras/quartus/xlr8_top_core.qsf
# Top level rtl, etc.
set_global_assignment -name TOP_LEVEL_ENTITY Retro_uC_top
set_global_assignment -name TOP_LEVEL_ENTITY Retro_uC_XLR8
# Simulation setup
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_sim -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH XLR8_tb -section_id eda_simulation
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name DEVICE 10M08SAU169C8G
set_global_assignment -name FAMILY "MAX 10"
......@@ -104,6 +104,9 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to TX
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RX
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to D2
......@@ -139,13 +142,10 @@ set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SOIC3
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SOIC2
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to SOIC1
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RESET_N
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_NAME top_sim -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id top_sim
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Retro_uC_top_sim -section_id top_sim
set_global_assignment -name EDA_TEST_BENCH_FILE "../../../rtl/vhdl/Retro_uC_top_sim.vhdl" -section_id top_sim
set_global_assignment -name EDA_TEST_BENCH_NAME XLR8_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id XLR8_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Retro_uC_XLR8_tb -section_id XLR8_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../rtl/vhdl/Retro_uC_XLR8_tb.vhdl -section_id XLR8_tb -hdl_version VHDL_2008
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_tap_fsm.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_tap_controller.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/c4m_jtag/rtl/vhdl/c4m_jtag_pkg.vhdl
......@@ -160,12 +160,14 @@ set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80_R
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/rtl/vhdl/T80s.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/submodules/t80/bench/vhdl/ROM80.vhd
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/Retro_uC.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/Retro_uC_wbbus.vhdl"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC.vhdl
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_wbbus.vhdl
set_global_assignment -name QIP_FILE xlr8_ram.qip
set_global_assignment -name VHDL_FILE ../rtl/vhdl/Retro_uC_ram.vhdl
set_global_assignment -name QSYS_FILE altera_dual_conf.qsys
set_global_assignment -name VHDL_FILE altera_dual_conf/synthesis/altera_dual_conf.vhd
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/Retro_uC_top.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/vhdl/Retro_uC_top_sim.vhdl"
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Retro_uC_top.vhdl
set_global_assignment -name VHDL_FILE ../rtl/vhdl/Retro_uC_XLR8.vhdl
set_global_assignment -name SDC_FILE "Retro-uC.sdc"
set_global_assignment -name VHDL_TEST_BENCH_FILE ../rtl/vhdl/Retro_uC_XLR8_tb.vhdl
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- Top Retro_uC block
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.c4m_jtag.ALL;
entity Retro_uC_XLR8 is
generic (
WITH_DUAL_CONFIG: boolean := true
);
port (
Clock: in std_logic;
RESET_N: in std_logic;
RX: inout std_logic;
TX: inout std_logic;
D2: inout std_logic;
D3: inout std_logic;
D4: inout std_logic;
D5: inout std_logic;
D6: inout std_logic;
D7: inout std_logic;
D8: inout std_logic;
D9: inout std_logic;
D10: inout std_logic;
D11: inout std_logic;
D12: inout std_logic;
D13: inout std_logic;
-- On Arduino D13 and LED are the same
-- XLR8 separates them
PIN13LED: out std_logic;
SDA: inout std_logic;
SCL: inout std_logic;
-- Enable pullups on sda/scl
-- '0'=disable, '1'=enable
I2C_ENABLE: out std_logic;
A0: inout std_logic;
A1: inout std_logic;
A2: inout std_logic;
A3: inout std_logic;
A4: inout std_logic;
A5: inout std_logic;
-- Disconnect Ana_Dig from ADC input
-- Put to '0' to disconnect, otherwise put to 'Z'
DIG_IO_OE: inout std_logic_vector(5 downto 0);
-- Choose ADC ref
-- '1'=AREF, '0'=regulated 3.3V
ANA_UP: out std_logic;
-- XLR8 JTAG header
JT1: inout std_logic; -- external pulldown, TCK
--JT2: GND
JT3: inout std_logic; -- TDO
--JT4: VREF
JT5: inout std_logic; -- external pullup, TMS
JT6: inout std_logic; -- TRST_N (optional)
JT7: inout std_logic; -- NC
--JT8: 5V
JT9: inout std_logic; -- external pullup, TDI
--JT10: GND
-- XLR8 SOIC-8 spot
SOIC1: inout std_logic;
SOIC2: inout std_logic;
SOIC3: inout std_logic;
--SOIC4
SOIC5: inout std_logic;
SOIC6: inout std_logic;
SOIC7: inout std_logic
--SOIC8
);
end Retro_uC_XLR8;
architecture rtl of Retro_uC_XLR8 is
-- IO signal for TAP
-- 0-13: DIG
-- 14-19: ANA
-- 20/21: SCL/SDA
-- other signal not currently handled by JTAG, directly connected
constant IOS: integer := 22;
signal IO_IN: std_logic_vector(IOS-1 downto 0);
signal IO_OUT: std_logic_vector(IOS-1 downto 0);
signal IO_EN: std_logic_vector(IOS-1 downto 0);
-- External JTAG signals
signal TRST_N: std_logic;
signal TCK: std_logic;
signal TMS: std_logic;
signal TDI: std_logic;
signal TDO: std_logic;
-- On Arduino UNO D13 is also the on board LED
-- On XLR8 it can be driven separately
-- We use it to indicate JTAG/debug state
signal S_PIN13LED: std_logic;
-- blinking LED
signal blinkcounter: unsigned(22 downto 0);
begin
-- Alias/convert the inputs/outputs
IO_IN(0) <= RX;
RX <= IO_OUT(0) when IO_EN(0) = '1' else 'Z';
IO_IN(1) <= TX;
TX <= IO_OUT(1) when IO_EN(1) = '1' else 'Z';
IO_IN(2) <= D2;
D2 <= IO_OUT(2) when IO_EN(2) = '1' else 'Z';
IO_IN(3) <= D3;
D3 <= IO_OUT(3) when IO_EN(3) = '1' else 'Z';
IO_IN(4) <= D4;
D4 <= IO_OUT(4) when IO_EN(4) = '1' else 'Z';
IO_IN(5) <= D5;
D5 <= IO_OUT(5) when IO_EN(5) = '1' else 'Z';
IO_IN(6) <= D6;
D6 <= IO_OUT(6) when IO_EN(6) = '1' else 'Z';
IO_IN(7) <= D7;
D7 <= IO_OUT(7) when IO_EN(7) = '1' else 'Z';
IO_IN(8) <= D8;
D8 <= IO_OUT(8) when IO_EN(8) = '1' else 'Z';
IO_IN(9) <= D9;
D9 <= IO_OUT(9) when IO_EN(9) = '1' else 'Z';
IO_IN(10) <= D10;
D10 <= IO_OUT(10) when IO_EN(10) = '1' else 'Z';
IO_IN(11) <= D11;
D11 <= IO_OUT(11) when IO_EN(11) = '1' else 'Z';
IO_IN(12) <= D12;
D12 <= IO_OUT(12) when IO_EN(12) = '1' else 'Z';
IO_IN(13) <= D13;
D13 <= IO_OUT(13) when IO_EN(13) = '1' else 'Z';
IO_IN(14) <= A0;
A0 <= IO_OUT(14) when IO_EN(14) = '1' else 'Z';
IO_IN(15) <= A1;
A1 <= IO_OUT(15) when IO_EN(15) = '1' else 'Z';
IO_IN(16) <= A2;
A2 <= IO_OUT(16) when IO_EN(16) = '1' else 'Z';
IO_IN(17) <= A3;
A3 <= IO_OUT(17) when IO_EN(17) = '1' else 'Z';
IO_IN(18) <= A4;
A4 <= IO_OUT(18) when IO_EN(18) = '1' else 'Z';
IO_IN(19) <= A5;
A5 <= IO_OUT(19) when IO_EN(19) = '1' else 'Z';
IO_IN(20) <= SCL;
SCL <= IO_OUT(20) when IO_EN(20) = '1' else 'Z';
IO_IN(21) <= SDA;
SDA <= IO_OUT(21) when IO_EN(21) = '1' else 'Z';
-- Forget about ADC for now
DIG_IO_OE <= "000000";
ANA_UP <= '0';
-- Do not enable I2C pull-up
I2C_ENABLE <= '0';
JT1 <= 'Z';
TCK <= JT1;
JT3 <= TDO;
JT5 <= 'Z';
TMS <= JT5;
JT6 <= 'Z';
JT7 <= 'Z';
JT9 <= 'Z';
TDI <= JT9;
-- No separate reset, use RESET_N as SRST of JTAG
TRST_N <= RESET_N;
-- No SOIC connection
SOIC1 <= 'Z';
SOIC2 <= 'Z';
SOIC3 <= 'Z';
SOIC5 <= 'Z';
SOIC6 <= 'Z';
SOIC7 <= 'Z';
-- Instantiate the Retro-uC top cell
Top: entity work.Retro_uC_top
generic map (
IOS => 22
)
port map (
Clock => Clock,
RESET_N => RESET_N,
TRST_N => TRST_N,
TCK => TCK,
TMS => TMS,
TDI => TDI,
TDO => TDO,
IO_IN => IO_IN,
IO_OUT => IO_OUT,
IO_EN => IO_EN
);
-- Blink LED13PIN @ 1Hz to indicate custom config
process (Clock, RESET_N)
begin
if RESET_N = '0' then
blinkcounter <= to_unsigned(1, 23);
S_PIN13LED <= '0';
elsif Rising_Edge(Clock) then
blinkcounter <= blinkcounter + 1;
if blinkcounter = 0 then
S_PIN13LED <= not S_PIN13LED;
end if;
end if;
end process;
PIN13LED <= S_PIN13LED;
DualOpt: if WITH_DUAL_CONFIG generate
-- dual config has to be instantiated or Quartus will complain
dual_conf: entity work.altera_dual_conf
port map (
avmm_rcv_address => (others => '0'),
avmm_rcv_read => '0',
avmm_rcv_writedata => (others => '0'),
avmm_rcv_write => '0',
avmm_rcv_readdata => open,
clk => Clock,
nreset => RESET_N
);
end generate;
end rtl;
......@@ -2,17 +2,20 @@ library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity Retro_uC_top_sim is
end Retro_uC_top_sim;
entity Retro_uC_XLR8_tb is
end Retro_uC_XLR8_tb;
architecture rtl of Retro_uC_top_sim is
architecture rtl of Retro_uC_XLR8_tb is
signal Clock: std_logic;
signal RESET_N: std_logic;
shared variable Running: boolean := true;
constant Period: time := 1us;
begin
Top: entity work.Retro_uC_top
Top: entity work.Retro_uC_XLR8
generic map (
WITH_DUAL_CONFIG => false
)
port map (
Clock => Clock,
RESET_N => RESET_N
......
-- The Retro_uC RAM for the XLR8 board
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Retro_uC_RAM is
port (
Clock: in std_logic;
CE: in std_logic;
WE: in std_logic;
Address: in std_logic_vector(12 downto 0);
Data_In: in std_logic_vector(7 downto 0);
Data_Out: out std_logic_vector(7 downto 0)
);
end entity Retro_uC_RAM;
architecture rtl of Retro_uC_RAM is
begin
XLR8RAM: entity work.xlr8_ram
port map (
address => Address,
clken => CE,
clock => Clock,
data => Data_In,
wren => WE,
q => Data_Out
);
end architecture rtl;
-- The Retro_uC generic RAM block
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Retro_uC_RAM is
port (
Clock: in std_logic;
CE: in std_logic;
WE: in std_logic;
-- Width of address will determine number of words in the RAM
Address: in std_logic_vector;
-- Data_In and Data_Out have to have the same width
Data_In: in std_logic_vector;
Data_Out: out std_logic_vector
);
end entity Retro_uC_RAM;
architecture rtl of Retro_uC_RAM is
type ram_type is array (0 to (2**Address'length)-1) of std_logic_vector(Data_In'range);
signal RAM: ram_type;
signal Address_hold: std_logic_vector(Address'range);
signal WE_hold: std_logic;
begin
process(Clock) is
begin
if (rising_edge(Clock) and CE = '1') then
if WE = '0' then
-- Read cycle
Data_Out <= RAM(to_integer(unsigned(Address)));
else
-- Write cycle
RAM(to_integer(unsigned(Address))) <= Data_In;
Data_Out <= Data_In;
end if;
end if;
end process;
end architecture rtl;
......@@ -7,92 +7,30 @@ use ieee.numeric_std.ALL;
use work.c4m_jtag.ALL;
entity Retro_uC_top is
generic (
IOS: integer := 1024
);
port (
Clock: in std_logic;
RESET_N: in std_logic;
RX: inout std_logic;
TX: inout std_logic;
D2: inout std_logic;
D3: inout std_logic;
D4: inout std_logic;
D5: inout std_logic;
D6: inout std_logic;
D7: inout std_logic;
D8: inout std_logic;
D9: inout std_logic;
D10: inout std_logic;
D11: inout std_logic;
D12: inout std_logic;
D13: inout std_logic;
-- On Arduino D13 and LED are the same
-- XLR8 separates them
PIN13LED: out std_logic;
SDA: inout std_logic;
SCL: inout std_logic;
-- Enable pullups on sda/scl
-- '0'=disable, '1'=enable
I2C_ENABLE: out std_logic;
A0: inout std_logic;
A1: inout std_logic;
A2: inout std_logic;
A3: inout std_logic;
A4: inout std_logic;
A5: inout std_logic;
-- Disconnect Ana_Dig from ADC input
-- Put to '0' to disconnect, otherwise put to 'Z'
DIG_IO_OE: inout std_logic_vector(5 downto 0);
-- Choose ADC ref
-- '1'=AREF, '0'=regulated 3.3V
ANA_UP: out std_logic;
-- JTAG interface
TRST_N: in std_logic;
TCK: in std_logic;
TMS: in std_logic;
TDI: in std_logic;
TDO: out std_logic;
-- XLR8 JTAG header
JT1: inout std_logic; -- external pulldown, TCK
--JT2: GND
JT3: inout std_logic; -- TDO
--JT4: VREF
JT5: inout std_logic; -- external pullup, TMS
JT6: inout std_logic; -- TRST_N (optional)
JT7: inout std_logic; -- NC
--JT8: 5V
JT9: inout std_logic; -- external pullup, TDI
--JT10: GND
-- XLR8 SOIC-8 spot
SOIC1: inout std_logic;
SOIC2: inout std_logic;
SOIC3: inout std_logic;
--SOIC4
SOIC5: inout std_logic;
SOIC6: inout std_logic;
SOIC7: inout std_logic
--SOIC8
IO_IN: in std_logic_vector(IOS-1 downto 0);
IO_OUT: out std_logic_vector(IOS-1 downto 0);
IO_EN: out std_logic_vector(IOS-1 downto 0)
);
end Retro_uC_top;
architecture rtl of Retro_uC_top is
-- IO signal for TAP
-- 0-13: DIG
-- 14-19: ANA
-- 20/21: SCL/SDA
-- other signal not currently handled by JTAG, directly connected
constant IOS: integer := 22;
signal CORE_IN: std_logic_vector(0 to IOS-1);
signal CORE_OUT: std_logic_vector(0 to IOS-1);
signal CORE_EN: std_logic_vector(0 to IOS-1);
signal PAD_IN: std_logic_vector(0 to IOS-1);
signal PAD_OUT: std_logic_vector(0 to IOS-1);
signal PAD_EN: std_logic_vector(0 to IOS-1);
-- External JTAG signals
signal TRST_N: std_logic;
signal TCK: std_logic;
signal TMS: std_logic;
signal TDI: std_logic;
signal TDO: std_logic;
signal CORE_IN: std_logic_vector(IOS-1 downto 0);
signal CORE_OUT: std_logic_vector(IOS-1 downto 0);
signal CORE_EN: std_logic_vector(IOS-1 downto 0);
-- Other TAP signals
signal TAP_STATE: TAPSTATE_TYPE;
......@@ -110,13 +48,6 @@ architecture rtl of Retro_uC_top is
signal ISWRITECMD: boolean;
signal ISMEMCMD: boolean;
-- On Arduino UNO D13 is also the on board LED
-- On XLR8 it can be driven separately
-- We use it to indicate JTAG/debug state
signal S_PIN13LED: std_logic;
-- blinking LED
signal blinkcounter: unsigned(22 downto 0);
-- Z80 signals
signal Z80_WB_Adr_o: std_logic_vector(15 downto 0);
signal Z80_WB_Dat_o: std_logic_vector(7 downto 0);
......@@ -156,81 +87,6 @@ architecture rtl of Retro_uC_top is
signal Bus_IOs_En: std_logic_vector(IOS-1 downto 0);
signal Bus_IOs_In: std_logic_vector(IOS-1 downto 0);
begin
-- Alias/convert the inputs/outputs
PAD_IN(0) <= RX;
RX <= PAD_OUT(0) when PAD_EN(0) = '1' else 'Z';
PAD_IN(1) <= TX;
TX <= PAD_OUT(1) when PAD_EN(1) = '1' else 'Z';
PAD_IN(2) <= D2;
D2 <= PAD_OUT(2) when PAD_EN(2) = '1' else 'Z';
PAD_IN(3) <= D3;
D3 <= PAD_OUT(3) when PAD_EN(3) = '1' else 'Z';
PAD_IN(4) <= D4;
D4 <= PAD_OUT(4) when PAD_EN(4) = '1' else 'Z';
PAD_IN(5) <= D5;
D5 <= PAD_OUT(5) when PAD_EN(5) = '1' else 'Z';
PAD_IN(6) <= D6;
D6 <= PAD_OUT(6) when PAD_EN(6) = '1' else 'Z';
PAD_IN(7) <= D7;
D7 <= PAD_OUT(7) when PAD_EN(7) = '1' else 'Z';
PAD_IN(8) <= D8;
D8 <= PAD_OUT(8) when PAD_EN(8) = '1' else 'Z';
PAD_IN(9) <= D9;
D9 <= PAD_OUT(9) when PAD_EN(9) = '1' else 'Z';
PAD_IN(10) <= D10;
D10 <= PAD_OUT(10) when PAD_EN(10) = '1' else 'Z';
PAD_IN(11) <= D11;
D11 <= PAD_OUT(11) when PAD_EN(11) = '1' else 'Z';
PAD_IN(12) <= D12;
D12 <= PAD_OUT(12) when PAD_EN(12) = '1' else 'Z';
PAD_IN(13) <= D13;
D13 <= PAD_OUT(13) when PAD_EN(13) = '1' else 'Z';
PAD_IN(14) <= A0;
A0 <= PAD_OUT(14) when PAD_EN(14) = '1' else 'Z';
PAD_IN(15) <= A1;
A1 <= PAD_OUT(15) when PAD_EN(15) = '1' else 'Z';
PAD_IN(16) <= A2;
A2 <= PAD_OUT(16) when PAD_EN(16) = '1' else 'Z';
PAD_IN(17) <= A3;
A3 <= PAD_OUT(17) when PAD_EN(17) = '1' else 'Z';
PAD_IN(18) <= A4;
A4 <= PAD_OUT(18) when PAD_EN(18) = '1' else 'Z';
PAD_IN(19) <= A5;
A5 <= PAD_OUT(19) when PAD_EN(19) = '1' else 'Z';
PAD_IN(20) <= SCL;
SCL <= PAD_OUT(20) when PAD_EN(20) = '1' else 'Z';
PAD_IN(21) <= SDA;
SDA <= PAD_OUT(21) when PAD_EN(21) = '1' else 'Z';
-- Forget about ADC for now
DIG_IO_OE <= "000000";
ANA_UP <= '0';
-- Do not enable I2C pull-up
I2C_ENABLE <= '0';
JT1 <= 'Z';
TCK <= JT1;
JT3 <= TDO;
JT5 <= 'Z';
TMS <= JT5;
JT6 <= 'Z';
JT7 <= 'Z';
JT9 <= 'Z';
TDI <= JT9;
-- No separate reset, use RESET_N as SRST of JTAG
TRST_N <= RESET_N;
-- No SOIC connection
SOIC1 <= 'Z';
SOIC2 <= 'Z';
SOIC3 <= 'Z';
SOIC5 <= 'Z';
SOIC6 <= 'Z';
SOIC7 <= 'Z';
-- Instantiate the microcontroller
Z80Core: entity work.Retro_uC
port map (
......@@ -266,9 +122,9 @@ begin
CORE_IN => CORE_IN,
CORE_EN => CORE_EN,
CORE_OUT => CORE_OUT,
PAD_IN => PAD_IN,
PAD_EN => PAD_EN,
PAD_OUT => PAD_OUT
PAD_IN => IO_IN,
PAD_EN => IO_EN,
PAD_OUT => IO_OUT
);
-- The Bus
......@@ -312,41 +168,41 @@ begin
Bus_BusMode <= '0';
-- Embedded SRAM
RAM0: entity work.xlr8_ram
RAM0: entity work.Retro_uC_RAM
port map (
address => Bus_Mem_Addr,
clken => Bus_Mem0_CE,
clock => Clock,
data => Bus_Mem0_Write_Data,
wren => Bus_Mem_WE,
q => Bus_Mem0_Read_Data
Clock => Clock,
CE => Bus_Mem0_CE,
WE => Bus_Mem_WE,
Address => Bus_Mem_Addr,
Data_In => Bus_Mem0_Write_Data,
Data_Out => Bus_Mem0_Read_Data
);
RAM1: entity work.xlr8_ram
RAM1: entity work.Retro_uC_RAM
port map (
address => Bus_Mem_Addr,
clken => Bus_Mem1_CE,
clock => Clock,
data => Bus_Mem1_Write_Data,
wren => Bus_Mem_WE,
q => Bus_Mem1_Read_Data
Clock => Clock,
CE => Bus_Mem1_CE,
WE => Bus_Mem_WE,
Address => Bus_Mem_Addr,
Data_In => Bus_Mem1_Write_Data,
Data_Out => Bus_Mem1_Read_Data
);
RAM2: entity work.xlr8_ram
RAM2: entity work.Retro_uC_RAM
port map (
address => Bus_Mem_Addr,
clken => Bus_Mem2_CE,
clock => Clock,
data => Bus_Mem2_Write_Data,
wren => Bus_Mem_WE,
q => Bus_Mem2_Read_Data
Clock => Clock,
CE => Bus_Mem2_CE,
WE => Bus_Mem_WE,
Address => Bus_Mem_Addr,
Data_In => Bus_Mem2_Write_Data,
Data_Out => Bus_Mem2_Read_Data
);
RAM3: entity work.xlr8_ram
RAM3: entity work.Retro_uC_RAM
port map (
address => Bus_Mem_Addr,
clken => Bus_Mem3_CE,
clock => Clock,
data => Bus_Mem3_Write_Data,
wren => Bus_Mem_WE,
q => Bus_Mem3_Read_Data
Clock => Clock,
CE => Bus_Mem3_CE,
WE => Bus_Mem_WE,
Address => Bus_Mem_Addr,
Data_In => Bus_Mem3_Write_Data,
Data_Out => Bus_Mem3_Read_Data
);
-- Z80 Retro-uC core is connected directly to WBBus
......@@ -419,37 +275,4 @@ begin
-- A => A(14 downto 0),
-- D => D
-- );
-- Blink LED13PIN @ 1Hz to indicate custom config
process (Clock, RESET_N, TAP_STATE)
begin
if RESET_N = '0' then
blinkcounter <= to_unsigned(1, 23);
S_PIN13LED <= '0';
elsif Rising_Edge(Clock) then
if TAP_STATE = TestLogicReset or TAP_STATE = RunTestIdle then
-- When TAP is in reset state LED is mirroring D13
S_PIN13LED <= D13;
else
blinkcounter <= blinkcounter + 1;
if blinkcounter = 0 then
S_PIN13LED <= not S_PIN13LED;
end if;
end if;
end if;
end process;
PIN13LED <= S_PIN13LED;
-- dual config has to be instantiated or Quartus will complain
dual_conf: entity work.altera_dual_conf
port map (
avmm_rcv_address => (others => '0'),
avmm_rcv_read => '0',
avmm_rcv_writedata => (others => '0'),
avmm_rcv_write => '0',
avmm_rcv_readdata => open,
clk => Clock,
nreset => RESET_N
);
end rtl;
PWD=$(realpath .)
TOPDIR=$(realpath ../../..)
RTLDIR=$(TOPDIR)/rtl
VHDLDIR=$(RTLDIR)/vhdl
T80VHDLDIR=$(RTLDIR)/submodules/t80/rtl/vhdl
C4MJTAGVHDLDIR=$(RTLDIR)/submodules/c4m_jtag/rtl/vhdl