Commit 08a6f51c authored by Fatsie's avatar Fatsie

XLR8: Added demo so leds on D2-D9 will blink in different ways.

4 ways:
 - JTAG boundary scan
 - JTAG memory access
 - Z80 program uploaded through JTAG
 - MOS6502 program uploaded through JTAG
parent e00cbe88
......@@ -23,5 +23,6 @@ synthesis
layout
Gerber*
boards/cloudv/rtl/verilog/Retro_uC_CloudV.ys
.compile
*.qws
.qsys_edit
! Read write from memory
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!MEMADDR => 256
SIR 3 TDI (3);
SDR 16 TDI (0010);
!WRITE => 0, 1, 2, 3
SIR 3 TDI (6);
SDR 32 TDI (0);
SDR 32 TDI (1);
SDR 32 TDI (2);
SDR 32 TDI (3);
!MEMADDR => 256
SIR 3 TDI (3);
SDR 16 TDI (0010) TDO (0014);
!READ; READ => 0, 1, 2 & 3
SIR 3 TDI (5);
SDR 32 TDI (0) TDO (0);
SDR 32 TDI (0) TDO (1);
SDR 32 TDI (0) TDO (2);
SDR 32 TDI (0) TDO (3);
!MEMADDR => 256
SIR 3 TDI (3);
SDR 16 TDI (0010) TDO (0014);
!RW; READ => 0, 1, 2 & 3; WRITE => 66666666, CCCCCCCC, 66666666 & CCCCCCCC;
SIR 3 TDI (6);
SDR 32 TDI (66666666) TDO (0);
SDR 32 TDI (CCCCCCCC) TDO (1);
SDR 32 TDI (66666666) TDO (2);
SDR 32 TDI (CCCCCCCC) TDO (3);
!MEMADDR => 256
SIR 3 TDI (3);
SDR 16 TDI (0010) TDO (0014);
!READ; READ => 66666666, CCCCCCCC, 66666666 & CCCCCCCC;
SIR 3 TDI (5);
SDR 32 TDI (0) TDO (66666666);
SDR 32 TDI (0) TDO (CCCCCCCC);
SDR 32 TDI (0) TDO (66666666);
SDR 32 TDI (0) TDO (CCCCCCCC);
STATE RESET;
! Blink the leds
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!SAMPLEPRELOAD instruction
SIR 3 TDI (1);
SDR 96 TDI (6DB6DB6DB6DB6DB6DB6DB6DB);
RUNTEST 2.0 SEC;
!EXTEST instruction
SIR 3 TDI (0);
SDR 96 TDI (249249249249249249249249);
RUNTEST 2.0 SEC;
SDR 96 TDI (6DB6DB6DB6DB6DB6DB6DB6DB);
RUNTEST 2.0 SEC;
SDR 96 TDI (249249249249249249249249);
RUNTEST 2.0 SEC;
SDR 96 TDI (6DB6DB6DB6DB6DB6DB6DB6DB);
RUNTEST 2.0 SEC;
SDR 96 TDI (249249249249249249249249);
RUNTEST 2.0 SEC;
SDR 96 TDI (6DB6DB6DB6DB6DB6DB6DB6DB);
RUNTEST 2.0 SEC;
SDR 96 TDI (249249249249249249249249);
RUNTEST 2.0 SEC;
SDR 96 TDI (6DB6DB6DB6DB6DB6DB6DB6DB);
RUNTEST 2.0 SEC;
SDR 96 TDI (249249249249249249249249);
RUNTEST 2.0 SEC;
STATE RESET;
! Blink the leds
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!Put first 32 IO to off
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000);
!WRITE => 0: all off
SIR 3 TDI (6);
SDR 32 TDI (0);
!Enable the first 32 IO outputs
!MEMADDR => start IO: 0010000000010000
SIR 3 TDI (3);
SDR 16 TDI (2020) TDO (2001);
!WRITE => FFFF: all enabled
SIR 3 TDI (6);
SDR 32 TDI (FFFF);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Enable D2-D9
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2021);
!WRITE => 0000001111111100: D2-D9 on
SIR 3 TDI (6);
SDR 32 TDI (000003FC);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Put first 32 IO to off
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2001);
!WRITE => 0: all off
SIR 3 TDI (6);
SDR 32 TDI (0);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Enable D2-D9
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2001);
!WRITE => 0000001111111100: D2-D9 on
SIR 3 TDI (6);
SDR 32 TDI (000003FC);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Put first 32 IO to off
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2001);
!WRITE => 0: all off
SIR 3 TDI (6);
SDR 32 TDI (0);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Enable D3, D5, D7 & D9
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2001);
!WRITE => 0000001010101000: D3, D5, D7 & D9 on
SIR 3 TDI (6);
SDR 32 TDI (000002A8);
! Wait 2 seconds
RUNTEST 2.0 SEC;
!Enable D2, D4, D6 & D7
!MEMADDR => start IO: 0010000000000000
SIR 3 TDI (3);
SDR 16 TDI (2000) TDO (2001);
!WRITE => 0000000101010100: D2, D4, D6 & D8 on
SIR 3 TDI (6);
SDR 32 TDI (00000154);
! Wait 2 seconds
RUNTEST 2.0 SEC;
STATE RESET;
#
# Buspirate with OpenOCD support
#
# http://dangerousprototypes.com/bus-pirate-manual/
#
interface buspirate
# you need to specify port on which BP lives
#buspirate_port /dev/ttyUSB0
buspirate_port /dev/buspirate
# communication speed setting
buspirate_speed normal ;# or fast
# voltage regulator Enabled = 1 Disabled = 0
#buspirate_vreg 0
# pin mode normal or open-drain
#buspirate_mode normal
# pullup state Enabled = 1 Disabled = 0
#buspirate_pullup 0
# this depends on the cable, you are safe with this option
reset_config srst_only
#!/bin/env python
import sys
head = \
"""TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!Disable cores
SIR 3 TDI (4);
SDR 2 TDI (0);
!Jump to $0200
!MEMADDR => 0
SIR 3 TDI (3);
SDR 16 TDI (0);
!WRITE
SIR 3 TDI (6);
SDR 32 TDI (0002004C);
!Load program from address 0200
!MEMADDR => 0080 (0080 in 32 bit is 0200 in 8 bit mode)
SIR 3 TDI (3);
SDR 16 TDI (0080);
!WRITE
SIR 3 TDI (6);
"""
tail = \
"""
!Enable MOS6502
SIR 3 TDI (4);
SDR 2 TDI (1);
STATE RESET;
"""
# Read input file
binfile = open(sys.argv[1], 'r')
blob = binfile.read()
blob_length = len(blob)
blob_words = blob_length/4
blob_mod = blob_length%4
binfile.close()
# Write output file
svffile = open(sys.argv[2], 'w')
svffile.write(head)
for i in range(blob_words):
svffile.write("SDR 32 TDI ({:02X}{:02X}{:02X}{:02X});\n".format(
ord(blob[i*4+3]), ord(blob[i*4+2]), ord(blob[i*4+1]), ord(blob[i*4])
))
# Write remaining bytes
if blob_mod > 0:
svffile.write("SDR 32 TDI (00{:02X}{:02X}{:02X});\n".format(
ord(blob[blob_words*4+2]) if blob_mod == 3 else 0,
ord(blob[blob_words*4+1]) if blob_mod >= 2 else 0,
ord(blob[blob_words*4])
))
svffile.write(tail)
svffile.close()
#!/bin/env python
import sys
head = \
"""TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!Disable cores
SIR 3 TDI (4);
SDR 2 TDI (0);
!Load program from address 0
!MEMADDR => 0
SIR 3 TDI (3);
SDR 16 TDI (0);
!WRITE
SIR 3 TDI (6);
"""
tail = \
"""
!Enable Z80
SIR 3 TDI (4);
SDR 2 TDI (2);
STATE RESET;
"""
# Read input file
binfile = open(sys.argv[1], 'r')
blob = binfile.read()
blob_length = len(blob)
blob_words = blob_length/4
blob_mod = blob_length%4
binfile.close()
# Write output file
svffile = open(sys.argv[2], 'w')
svffile.write(head)
for i in range(blob_words):
svffile.write("SDR 32 TDI ({:02X}{:02X}{:02X}{:02X});\n".format(
ord(blob[i*4+3]), ord(blob[i*4+2]), ord(blob[i*4+1]), ord(blob[i*4])
))
# Write remaining bytes
if blob_mod > 0:
svffile.write("SDR 32 TDI (00{:02X}{:02X}{:02X});\n".format(
ord(blob[blob_words*4+2]) if blob_mod == 3 else 0,
ord(blob[blob_words*4+1]) if blob_mod >= 2 else 0,
ord(blob[blob_words*4])
))
svffile.write(tail)
svffile.close()
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!Disable cores
SIR 3 TDI (4);
SDR 2 TDI (0);
!Jump to $0200
!MEMADDR => 0
SIR 3 TDI (3);
SDR 16 TDI (0);
!WRITE
SIR 3 TDI (6);
SDR 32 TDI (0002004C);
!Load program from address 0200
!MEMADDR => 0080 (0080 in 32 bit is 0200 in 8 bit mode)
SIR 3 TDI (3);
SDR 16 TDI (0080);
!WRITE
SIR 3 TDI (6);
SDR 32 TDI (10A200A9);
SDR 32 TDI (81868085);
SDR 32 TDI (2003B520);
SDR 32 TDI (23200217);
SDR 32 TDI (CF204802);
SDR 32 TDI (A0606802);
SDR 32 TDI (A907F000);
SDR 32 TDI (4C02A223);
SDR 32 TDI (AD6003DC);
SDR 32 TDI (888503DA);
SDR 32 TDI (8503DBAD);
SDR 32 TDI (A0FFA989);
SDR 32 TDI (AD889100);
SDR 32 TDI (888503DA);
SDR 32 TDI (8503DBAD);
SDR 32 TDI (C8FFA989);
SDR 32 TDI (D8AD8891);
SDR 32 TDI (AD888503);
SDR 32 TDI (898503D9);
SDR 32 TDI (91A800A9);
SDR 32 TDI (03D8AD88);
SDR 32 TDI (D9AD8885);
SDR 32 TDI (98898503);
SDR 32 TDI (208891C8);
SDR 32 TDI (D8AD0287);
SDR 32 TDI (AD888503);
SDR 32 TDI (898503D9);
SDR 32 TDI (00A0FCA9);
SDR 32 TDI (D8AD8891);
SDR 32 TDI (AD888503);
SDR 32 TDI (898503D9);
SDR 32 TDI (91C803A9);
SDR 32 TDI (02872088);
SDR 32 TDI (2002424C);
SDR 32 TDI (00A002DB);
SDR 32 TDI (809170A9);
SDR 32 TDI (91C811A9);
SDR 32 TDI (91C89880);
SDR 32 TDI (C800A980);
SDR 32 TDI (AC4C8091);
SDR 32 TDI (8600A202);
SDR 32 TDI (A9838682);
SDR 32 TDI (03622001);
SDR 32 TDI (20032820);
SDR 32 TDI (00A2034A);
SDR 32 TDI (83868286);
SDR 32 TDI (033B208A);
SDR 32 TDI (E84CE3D0);
SDR 32 TDI (1848C802);
SDR 32 TDI (85806598);
SDR 32 TDI (E6029080);
SDR 32 TDI (A0606881);
SDR 32 TDI (A907F000);
SDR 32 TDI (4C03A2DC);
SDR 32 TDI (A56003DC);
SDR 32 TDI (04E93880);
SDR 32 TDI (01908085);
SDR 32 TDI (6081C660);
SDR 32 TDI (C24C04A0);
SDR 32 TDI (86888502);
SDR 32 TDI (B103A089);
SDR 32 TDI (83E53880);
SDR 32 TDI (B18822D0);
SDR 32 TDI (D082C580);
SDR 32 TDI (80B1880C);
SDR 32 TDI (05D089C5);
SDR 32 TDI (C580B188);
SDR 32 TDI (E8200888);
SDR 32 TDI (04F02802);
SDR 32 TDI (FFA903B0);
SDR 32 TDI (6001A960);
SDR 32 TDI (FF490450);
SDR 32 TDI (20080109);
SDR 32 TDI (602802E8);
SDR 32 TDI (80B103A0);
SDR 32 TDI (B1888385);
SDR 32 TDI (88828580);
SDR 32 TDI (88AA80B1);
SDR 32 TDI (206080B1);
SDR 32 TDI (894C02ED);
SDR 32 TDI (AA00A903);
SDR 32 TDI (828400A0);
SDR 32 TDI (20488384);
SDR 32 TDI (03A002DB);
SDR 32 TDI (809183A5);
SDR 32 TDI (9182A588);
SDR 32 TDI (918A8880);
SDR 32 TDI (91886880);
SDR 32 TDI (00A06080);
SDR 32 TDI (71FF4938);
SDR 32 TDI (48809180);
SDR 32 TDI (FF498AC8);
SDR 32 TDI (80918071);
SDR 32 TDI (80B1C8AA);
SDR 32 TDI (809182E5);
SDR 32 TDI (B1C88285);
SDR 32 TDI (9183E580);
SDR 32 TDI (68838580);
SDR 32 TDI (A206D060);
SDR 32 TDI (D0608A00);
SDR 32 TDI (A900A2FA);
SDR 32 TDI (F9F06001);
SDR 32 TDI (00A2F730);
SDR 32 TDI (02F0608A);
SDR 32 TDI (00A2EF10);
SDR 32 TDI (E9F0608A);
SDR 32 TDI (00A2E790);
SDR 32 TDI (DBF0608A);
SDR 32 TDI (2A8A00A2);
SDR 32 TDI (8501A960);
SDR 32 TDI (8504A988);
SDR 32 TDI (A800A989);
SDR 32 TDI (0AF000A2);
SDR 32 TDI (D0C88891);
SDR 32 TDI (CA89E6FB);
SDR 32 TDI (00C0F6D0);
SDR 32 TDI (889105F0);
SDR 32 TDI (60F7D0C8);
SDR 32 TDI (80808000);
SDR 32 TDI (8E03EA8D);
SDR 32 TDI (F18D03EB);
SDR 32 TDI (03F28E03);
SDR 32 TDI (FFFFB988);
SDR 32 TDI (8803FB8D);
SDR 32 TDI (8DFFFFB9);
SDR 32 TDI (FD8C03FA);
SDR 32 TDI (FFFF2003);
SDR 32 TDI (E8D0FFA0);
SDR 32 TDI (00000060);
!Enable MOS6502
SIR 3 TDI (4);
SDR 2 TDI (1);
STATE RESET;
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
!Disable cores
SIR 3 TDI (4);
SDR 2 TDI (0);
!Load program from address 0
!MEMADDR => 0
SIR 3 TDI (3);
SDR 16 TDI (0);
!WRITE
SIR 3 TDI (6);
SDR 32 TDI (2A200031);
SDR 32 TDI (FF36002E);
SDR 32 TDI (23002E2A);
SDR 32 TDI (2C2AFF36);
SDR 32 TDI (2A003600);
SDR 32 TDI (3623002C);
SDR 32 TDI (0030CD00);
SDR 32 TDI (36002C2A);
SDR 32 TDI (002C2AFC);
SDR 32 TDI (CD033623);
SDR 32 TDI (E2180030);
SDR 32 TDI (80808000);
SDR 32 TDI (01701111);
SDR 32 TDI (B0790100);
SDR 32 TDI (7AC8B2B3);
SDR 32 TDI (7B57FFC6);
SDR 32 TDI (785FFFCE);
SDR 32 TDI (7947FFCE);
SDR 32 TDI (184FFFCE);
SDR 32 TDI (0000C9E9);
!Enable Z80
SIR 3 TDI (4);
SDR 2 TDI (2);
STATE RESET;
#!/bin/sh
SDCC_PREFIX=sdcc-
SDCC=${SDCC_PREFIX}sdcc
MAKEBIN=${SDCC_PREFIX}makebin
CL65=cl65
rm -fr .compile
mkdir .compile
cd .compile
ln -s ../setleds.c .
$SDCC -mz80 --no-std-crt0 --code-loc 0 -DZ80 setleds.c
$MAKEBIN -p setleds.ihx setledsz80.bin
$CL65 -C ../retrino6502.cfg -t none -Oi -o setleds6502.bin setleds.c
cd ..
./bin2svf_z80.py .compile/setledsz80.bin blink_z80.svf
./bin2svf_mos6502.py .compile/setleds6502.bin blink_mos6502.svf
FEATURES {
STARTADDRESS: default = $0200;
}
SYMBOLS {
__STACKSIZE__: type = weak, value = $0400; # 1k stack
__STACKSTART__: type = weak, value = $1000;
__ZPSTART__: type = weak, value = $0080;
}
MEMORY {
ZP: file = "", define = yes, start = __ZPSTART__, size = $001F;
MAIN: file = %O, start = %S, size = __STACKSTART__ - __STACKSIZE__ - %S;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp;
STARTUP: load = MAIN, type = ro, optional = yes;
LOWCODE: load = MAIN, type = ro, optional = yes;
ONCE: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = rw;
RODATA: load = MAIN, type = rw;
DATA: load = MAIN, type = rw;
BSS: load = MAIN, type = bss, define = yes;
}
FEATURES {
CONDES: type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__,
segment = ONCE;
CONDES: type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__,
segment = RODATA;
CONDES: type = interruptor,
label = __INTERRUPTOR_TABLE__,
count = __INTERRUPTOR_COUNT__,
segment = RODATA,
import = __CALLIRQ__;
}
#include <stdint.h>
// Try to inline.
// SP does not work yet.
void main(void);
void wait(void);
char * const ioout = (char *)0x8000;
char * const ioen = (char *)0x8080;
void main(void)
{
// Initialize stack pointer
#if defined(Z80)
__asm
LD SP, #0x2000
__endasm;
#endif
// Enable the outputs
ioen[0] = 0xFF;
ioen[1] = 0xFF;
while(1)
{
// Put D0-D15 to 0
ioout[0] = 0x00;
ioout[1] = 0x00;
wait();
// Turn leds D2-D9 on
ioout[0] = 0xFC;
ioout[1] = 0x03;
wait();
}
}
void wait(void)
{
uint32_t value;
value = (uint32_t)70000;
while(value != 0)
--value;
return;
}
#!/bin/sh
echo $1
openocd -f ./buspirate.cfg -c "init; svf \"$1\" ignore_error; shutdown"
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