* Arbiter adds wait state before and after the JTAG memory cycle
 * Wishbone interface of JTAG now runs on Clock not TCK
 * Neither T65 or T80 wait for ack to start new cycle.
 * T65 & T80 cpu is run on inverted clock to avoid need of wait state during read.
   This way address is update on falling clock edge, read data generated
   on rising edge and available for CPU on falling edge.
 * WBBus output the T65 Vector data after the clock cycle.
 * In JTAG_RAM cocotb sim write JTAG data not to address 0 as there code is
   located for the CPUs.